SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.3.2 System Registers

Table 8-10 lists the memory-mapped registers for the System registers. All register offset addresses not listed in Table 8-10 should be considered as reserved locations and the register contents should not be modified.

Table 8-10 SYSTEM Registers
OffsetAcronymRegister NameSection
0x20SYS_ENSection 8.3.2.1
0x21FR_ENSection 8.3.2.2
0x22PWR_RAMPSection 8.3.2.3
0x23PWR_IDLESection 8.3.2.4
0x24CMOS_BOOSTSection 8.3.2.5
0x25TX_EN_SELSection 8.3.2.6
0x26TX_ENSection 8.3.2.7
0x27TX_PIN_FUNCSection 8.3.2.8
0x28SYNCB_PIN_FUNCSection 8.3.2.9
0x2AAPP_SLEEP0Section 8.3.2.10
0x2BAPP_SLEEP1Section 8.3.2.11
0x2CAPP_SLEEP0_ENSection 8.3.2.12

Complex bit access types are encoded to fit into small table cells. Table 8-11 shows the codes that are used for access types in this section.

Table 8-11 System Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.3.2.1 SYS_EN Register (Offset = 0x20) [Reset = 0x00]

SYS_EN is shown in Table 8-12.

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Table 8-12 SYS_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0SYS_ENR/W0x0 When SYS_EN=0, all circuits operating from the DAC clock (with exception of the fuse controller) are held in reset. The clocks are gated off to save power. The LMFC/LEMC counter is also held in reset, so SYSREF will not align the LMFC/LEMC.
Note: This register should only be changed from 0 to 1 when FUSE_DONE=1.
Note: If CPLL_EN=1, this bit should not be set until CPLL_LOCKED=1.
  • 0x0 = Disable System Operation
  • 0x1 = Enable System Operation

8.3.2.2 FR_EN Register (Offset = 0x21) [Reset = 0x00]

FR_EN is shown in Table 8-13.

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Table 8-13 FR_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0FR_ENR/W0x0 The FRI utilizes the TRIG pins, making them unavailable for triggering DSPs. The user may use TX_PIN_FUNC or SYNCB_PIN_FUNC to assign other pins as trigger inputs.
Note: The TRIGCLK input should be static and TRIG[4] should be high for 30ns before and after changes to FR_EN.
Note: This register should only be changed when the FRI interface is idle.
  • 0x0 = FRI is disabled. PFIR and NCO parameters are controlled by SPI.
  • 0x1 = FRI is enabled. PFIR and NCO parameters are controlled by FRI.

8.3.2.3 PWR_RAMP Register (Offset = 0x22) [Reset = 0x00]

PWR_RAMP is shown in Table 8-14.

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Table 8-14 PWR_RAMP Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0x0
1-0PWR_RAMPR/W0x0 This register controls how the design ramps up power when digital components are enabled. Use this register to avoid large inrush current. Higher settings will reduce inrush current. The design will ramp up power as a result of any of these actions:
1) Setting SYS_EN=1
2) Adjusting MODE to a higher power state
3) Using pin to exit APP Sleep mode (see TX_PIN_FUNC / SYNCB_PIN_FUNC)
4)Taking components out of sleep mode via the APP_SLEEP0/1 functions.
Maximum time to wave all power zones:
0: 4376 DACCLK cycles
1: 20256 DACCLK cycles
2: 252576 DACCLK cycles
3: 3969696 DACCLK cycles

8.3.2.4 PWR_IDLE Register (Offset = 0x23) [Reset = 0x0X]

PWR_IDLE is shown in Table 8-15.

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Table 8-15 PWR_IDLE Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0PWR_IDLERX This returns a 1 when the power controller is idle (no power zones are in the process of turning on or off). This bit can also be driven onto the ALARM pin. See ALARM_TSEL.

8.3.2.5 CMOS_BOOST Register (Offset = 0x24) [Reset = 0x00]

CMOS_BOOST is shown in Table 8-16.

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Table 8-16 CMOS_BOOST Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0x0
1TRIGC_BOOSTR/W0x0 Enables the boost feature for the TRIGCLK output. Only has an effect when TRIGCLK is configured as an output pin.
0SDO_BOOSTR/W0x0 Enables the boost feature for the SDO output.

8.3.2.6 TX_EN_SEL Register (Offset = 0x25) [Reset = 0x00]

TX_EN_SEL is shown in Table 8-17.

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Table 8-17 TX_EN_SEL Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3IDLE_STATICR/W0x0 Selects the method that a DAC uses when transmission is disabled (via txenable or TX_EN)
  • 0x0 = Transmission is disabled after DEM and dither using the Aging Safe Static Outputs. For some configurations and frequencies, this will produce more noise on the DAC output than a static mid-scale code would normally produce. However, this mode has the lowest latency from transmit enable to DAC output.
  • 0x1 = Transmission is disabled by muting the input to DEM and dither to minimize the output noise. This increases the latency from transmit enable to DAC output (see Transmit Enable A/C Specs).
2-0RESERVEDR0x0

8.3.2.7 TX_EN Register (Offset = 0x26) [Reset = 0x00]

TX_EN is shown in Table 8-18.

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Table 8-18 TX_EN Register Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0x0
1TX_EN1R/W0x0 If low, DACB is muted according to IDLE_STATIC.
0TX_EN0R/W0x0 If low, DACA is muted according to IDLE_STATIC.

8.3.2.8 TX_PIN_FUNC Register (Offset = 0x27) [Reset = 0x00]

TX_PIN_FUNC is shown in Table 8-19.

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Table 8-19 TX_PIN_FUNC Register Field Descriptions
BitFieldTypeResetDescription
7-4TX_PIN_FUNC1R/W0x0 Defines the function of the TXENABLE[1] pin. These actions are applied when the pin is low.
Note: These settings can be used with TRIG_TYPEx=4. They provide alternate pins to drive the trigger system, but do not affect the FRI interface (FRI interface always uses the physical TRIG pins). Behavior is undefined if multiple pins are configured as an alternate input for the same TRIG[x] pin.
Note: This register should only be changed when SYS_EN=0.
  • 0x0 = Pin is ignored (default)
  • 0x1 = Mute DACA according to IDLE_STATIC value. Pin is active low.
  • 0x2 = Mute DACB according to IDLE_STATIC value. Pin is active low.
  • 0x3 = Mute DACA and DACB according to IDLE_STATIC value. Pin is active low.
  • 0x4 = Sleep entire application layer accouring the APP_SLEEP. Pin is active low.
  • 0x5 = Sleep entire application layer accouring the APP_SLEEP0. Pin is active low.
  • 0x6 = Sleep entire application layer accouring the APP_SLEEP1. Pin is active low.
  • 0x7 = Pin is apply DAC_SRC_ALT0 binding. Active low.
  • 0x8 = Apply DAC_SRC_ALT1 binding. Pin is active low.
  • 0x9 = Apply DAC_SRC_ALT0 and DAC_SRC_ALT1 bindings. Pin is active low.
  • 0xA = Alternate input for TRIG[0]. Can be used with TRIG_TYPEx is set to 4.
  • 0xB = Alternate input for TRIG[1]. Can be used with TRIG_TYPEx is set to 4.
  • 0xC = Alternate input for TRIG[2]. Can be used with TRIG_TYPEx is set to 4.
  • 0xD = RESERVED
  • 0xE = Mask over-range events. Pin is active low.
  • 0xF = RESERVED
3-0TX_PIN_FUNC0R/W0x0 Defines the function of the TXENABLE[0] pin. These actions are applied when the pin is low.
Note: These settings can be used with TRIG_TYPEx=4. They provide alternate pins to drive the trigger system, but do not affect the FRI interface (FRI interface always uses the physical TRIG pins). Behavior is undefined if multiple pins are configured as an alternate input for the same TRIG[x] pin.
Note: This register should only be changed when SYS_EN=0.
  • 0x0 = Pin is ignored (default)
  • 0x1 = Mute DACA according to IDLE_STATIC value. Pin is active low.
  • 0x2 = Mute DACB according to IDLE_STATIC value. Pin is active low.
  • 0x3 = Mute DACA and DACB according to IDLE_STATIC value. Pin is active low.
  • 0x4 = Sleep entire application layer accouring the APP_SLEEP. Pin is active low.
  • 0x5 = Sleep entire application layer accouring the APP_SLEEP0. Pin is active low.
  • 0x6 = Sleep entire application layer accouring the APP_SLEEP1. Pin is active low.
  • 0x7 = Apply DAC_SRC_ALT0 binding. Pin is active low.
  • 0x8 = Apply DAC_SRC_ALT1 binding. Pin is active low.
  • 0x9 = Apply DAC_SRC_ALT0 and DAC_SRC_ALT1 bindings. Pin is active low.
  • 0xA = Alternate input for TRIG[0]. Can be used with TRIG_TYPEx is set to 4.
  • 0xB = Alternate input for TRIG[1]. Can be used with TRIG_TYPEx is set to 4.
  • 0xC = Alternate input for TRIG[2]. Can be used with TRIG_TYPEx is set to 4.
  • 0xD = RESERVED
  • 0xE = Mask over-range events. Pin is active low.
  • 0xF = RESERVED

8.3.2.9 SYNCB_PIN_FUNC Register (Offset = 0x28) [Reset = 0x00]

SYNCB_PIN_FUNC is shown in Table 8-20.

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Table 8-20 SYNCB_PIN_FUNC Register Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0x0
3-0SYNCB_PIN_FUNCR/W0x0 Defines the function of the SYNCB pin when JENC=1 (64b/66b). When JENC=0 (8b/10b) this register has no effect (SYNCB is used by JESD interface).
These actions are applied when the pin is low. Note: These settings can be used with TRIG_TYPEx=4.
They provide alternate pins to drive the trigger system, but do not affect the FRI interface (FRI interface always uses the physical TRIG pins). Behavior is undefined if multiple pins are configured as an alternate input for the same TRIG[x] pin.
If the JESD interface is unused, all DSPs are in a DDS mode and JESD_M=0. However, you must still set JENC=1 to allow the SYNCB pin to be used as a input signal.
Note: This register should only be changed when SYS_EN=0.
  • 0x0 = Pin is ignored (default)
  • 0x1 = Mute DACA according to IDLE_STATIC value. Pin is active low.
  • 0x2 = Mute DACB according to IDLE_STATIC value. Pin is active low.
  • 0x3 = Mute DACA and DACB according to IDLE_STATIC value. Pin is active low.
  • 0x4 = Sleep entire application layer accouring the APP_SLEEP. Pin is active low.
  • 0x5 = Sleep entire application layer accouring the APP_SLEEP0. Pin is active low.
  • 0x6 = Sleep entire application layer accouring the APP_SLEEP1. Pin is active low.
  • 0x7 = Apply DAC_SRC_ALT0 binding. Pin is active low.
  • 0x8 = Apply DAC_SRC_ALT1 binding. Pin is active low.
  • 0x9 = Apply DAC_SRC_ALT0 and DAC_SRC_ALT1 bindings. Pin is active low.
  • 0xA = Alternate input for TRIG[0]. Can be used with TRIG_TYPEx is set to 4.
  • 0xB = Alternate input for TRIG[1]. Can be used with TRIG_TYPEx is set to 4.
  • 0xC = Alternate input for TRIG[2]. Can be used with TRIG_TYPEx is set to 4.
  • 0xD = RESERVED
  • 0xE = Mask over-range events. Pin is active low.
  • 0xF = RESERVED

8.3.2.10 APP_SLEEP0 Register (Offset = 0x2A) [Reset = 0x00]

APP_SLEEP0 is shown in Table 8-21.

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Table 8-21 APP_SLEEP0 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5DACB_SLEEP0R/W0x0 These bits control which components are put to sleep when a pin or register activates the APP_SLEEP0 function (see TX_PIN_FUNC, SYNCB_PIN_FUNC, APP_SLEEP0_EN).
Note: When APP_SLEEP0/APP_SLEEP1 function is deactivated, components are re-enabled gradually to prevent power supply brownout.
Note: When the MODE register is 1 or higher, the entire application layer is asleep, so this register has no effect.
Note: When a PFIR is producing samples for a DSP input, the PFIR channel is asleep when the DSP channel is asleep.
Note: When a PFIR is producing samples for an encoder, the PFIR channel is asleep when encoder is asleep:
Note: When PFIR channel 0 is broadcasting to both encoders, the PFIR is asleep only when both encoders are asleep (See PFIR_BC).
DACB is muted (according to IDLE_STATIC) and encoder 1 is asleep when the APP_SLEEP0 function is activated.
When a DSP is asleep, it can still process trigger events if the MODE register is configured for normal operation.
4DACA_SLEEP0R/W0x0 DACA is muted (according to IDLE_STATIC) and associated encoder is asleep when the APP_SLEEP0 function is activated.
Note: If the APP_SLEEP0 and APP_SLEEP1 functions are both active at the same time, then components are asleep if either function requests it (logical OR).
3DSP3_SLEEP0R/W0x0 DSP channel 3 is asleep when the APP_SLEEP0 function is activated.
2DSP2_SLEEP0R/W0x0 DSP channel 2 is asleep when the APP_SLEEP0 function is activated.
1DSP1_SLEEP0R/W0x0 DSP channel 1 is asleep when the APP_SLEEP0 function is activated.
0DSP0_SLEEP0R/W0x0 DSP channel 0 is asleep when the APP_SLEEP0 function is activated.

8.3.2.11 APP_SLEEP1 Register (Offset = 0x2B) [Reset = 0x00]

APP_SLEEP1 is shown in Table 8-22.

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Table 8-22 APP_SLEEP1 Register Field Descriptions
BitFieldTypeResetDescription
7-6RESERVEDR0x0
5DACB_SLEEP1R/W0x0 DACB is muted (according to IDLE_STATIC) and associated encoder is asleep when the APP_SLEEP1 function is activated. See notes for APP_SLEEP0.
4DACA_SLEEP1R/W0x0 DACA is muted (according to IDLE_STATIC) and encoder 0 is asleep when the APP_SLEEP1 function is activated.
3DSP3_SLEEP1R/W0x0 DSP channel 3 is asleep when the APP_SLEEP1 function is activated.
2DSP2_SLEEP1R/W0x0 DSP channel 2 is asleep when the APP_SLEEP1 function is activated.
1DSP1_SLEEP1R/W0x0 DSP channel 1 is asleep when the APP_SLEEP1 function is activated.
0DSP0_SLEEP1R/W0x0 DSP channel 0 is asleep when the APP_SLEEP1 function is activated.

8.3.2.12 APP_SLEEP0_EN Register (Offset = 0x2C) [Reset = 0x00]

APP_SLEEP0_EN is shown in Table 8-23.

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Table 8-23 APP_SLEEP0_EN Register Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0x0
0APP_SLEEP0_ENR/W0x0 When set, components are put to sleep according to the APP_SLEEP0 register. Use this when you want fine-grained control of application sleep, but do not want to dedicate a pin to activate it. You may leave this register set and modify the APP_SLEEP0 register to sleep/wake components on the fly (while SYS_EN=1).