SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5 Pin Configuration and Functions

DAC39RF20 ANH0289A Package, 289-Ball Flip Chip CSP with 0.8mm pitch (Top View) Figure 5-1 ANH0289A Package, 289-Ball Flip Chip CSP with 0.8mm pitch (Top View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO
DAC Outputs
DACOUTA- A13 O DAC channel A analog output negative terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance.
DACOUTA+ A11 O DAC channel A analog output positive terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance.
DACOUTB- U13 O DAC channel B analog output negative terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance.
DACOUTB+ U11 O DAC channel B analog output positive terminal. Output voltage must comply with DAC compliance voltage to maintain specified performance.
Differential Clock and SYSREF Inputs
CLK- P17 I Device clock input negative terminal. There is an internal 100Ω differential termination between CLK+ and CLK–. This input is self-biased and should be AC coupled to the clock source.
CLK+ N17 I Device clock input positive terminal. There is an internal 100Ω differential termination between CLK+ and CLK–. This input is self-biased and should be AC coupled to the clock source.
SYSREF- E17 I Differential JESD204C SYSREF input negative terminal. There is an internal 100Ω differential termination between SYSREF+ and SYSREF–. This input is self-biased if AC coupled. If DC coupled, the input common mode must meet the VCMI specification in Recommended Operating Conditions.
SYSREF+ D17 I Differential JESD204C SYSREF input negative terminal. There is an internal 100Ω differential termination between SYSREF+ and SYSREF–.
SerDes Interface
0SRX- A7 I Serdes Lane 0 negative input. Includes 100Ω internal termination to 0SRX+.
0SRX+ A8 I Serdes Lane 0 positive input. Includes 100Ω internal termination to 0SRX-.
1SRX- B7 I Serdes Lane 1 negative input. Includes 100Ω internal termination to 1SRX+.
1SRX+ B8 I Serdes Lane 1 positive input. Includes 100Ω internal termination to 1SRX-.
2SRX- A4 I Serdes Lane 2 negative input. Includes 100Ω internal termination to 2SRX+.
2SRX+ A5 I Serdes Lane 2 positive input. Includes 100Ω internal termination to 2SRX-.
3SRX- B4 I Serdes Lane 3 negative input. Includes 100Ω internal termination to 3SRX+.
3SRX+ B5 I Serdes Lane 3 positive input. Includes 100Ω internal termination to 3SRX-.
4SRX- D1 I Serdes Lane 4 negative input. Includes 100Ω internal termination to 4SRX+.
4SRX+ C1 I Serdes Lane 4 positive input. Includes 100Ω internal termination to 4SRX-.
5SRX- D2 I Serdes Lane 5 negative input. Includes 100Ω internal termination to 5SRX+.
5SRX+ C2 I Serdes Lane 5 positive input. Includes 100Ω internal termination to 5SRX-.
6SRX- G1 I Serdes Lane 6 negative input. Includes 100Ω internal termination to 6SRX+.
6SRX+ F1 I Serdes Lane 6 positive input. Includes 100Ω internal termination to 6SRX-.
7SRX- G2 I Serdes Lane 7 negative input. Includes 100Ω internal termination to 7SRX+.
7SRX+ F2 I Serdes Lane 7 positive input. Includes 100Ω internal termination to 7SRX-.
8SRX- U8 I Serdes Lane 8 negative input. Includes 100Ω internal termination to 8SRX+.
8SRX+ U7 I Serdes Lane 8 positive input. Includes 100Ω internal termination to 8SRX-.
9SRX- T8 I Serdes Lane 9 negative input. Includes 100Ω internal termination to 9SRX+.
9SRX+ T7 I Serdes Lane 9 positive input. Includes 100Ω internal termination to 9SRX-.
10SRX- U5 I Serdes Lane 10 negative input. Includes 100Ω internal termination to 10SRX+.
10SRX+ U4 I Serdes Lane 10 positive input. Includes 100Ω internal termination to 10SRX-.
11SRX- T5 I Serdes Lane 11 negative input. Includes 100Ω internal termination to 11SRX+.
11SRX+ T4 I Serdes Lane 11 positive input. Includes 100Ω internal termination to 11SRX-.
12SRX- R1 I Serdes Lane 12 negative input. Includes 100Ω internal termination to 12SRX+.
12SRX+ P1 I Serdes Lane 12 positive input. Includes 100Ω internal termination to 12SRX-.
13SRX- R2 I Serdes Lane 13 negative input. Includes 100Ω internal termination to 13SRX+.
13SRX+ P2 I Serdes Lane 13 positive input. Includes 100Ω internal termination to 13SRX-.
14SRX- M1 I Serdes Lane 14 negative input. Includes 100Ω internal termination to 14SRX+.
14SRX+ L1 I Serdes Lane 14 positive input. Includes 100Ω internal termination to 14SRX-.
15SRX- M2 I Serdes Lane 15 negative input. Includes 100Ω internal termination to 15SRX+.
15SRX+ L2 I Serdes Lane 15 positive input. Includes 100Ω internal termination to 15SRX-.
GPIO Functions
ALARM E3 O ALARM pin is asserted when an internal unmasked alarm is detected. Alarm mask is set by ALM_MASK register. No pullup or pulldown.
RESET E5 I Device reset input, active low. Must be toggled after power up. Internal pullup.
SCANEN F3 I TI use only, can be left unconnected. Internal pulldown.
SCLK J1 I Serial programming interface (SPI) clock input. No pullup or pulldown.
SCS K3 I Serial programming interface (SPI) device select input, active low. Internal pullup.
SDI J3 I Serial programming interface (SPI) data input. No pullup or pulldown.
SDO J2 O Serial programming interface (SPI) data output. High impedance when not reading out SPI data. No pullup or pulldown.
SYNC E4 I/O JESD204C SYNC output, active low. Pullup active when used as an input.
TRIG0 D9 I Trigger interface ball 0. Also used as data input 0 for FR Interface. Internal pulldown.
TRIG1 D8 I Trigger interface ball 1. Also used as data input 1 for FR Interface. Internal pulldown.
TRIG2 D7 I Trigger interface ball 2. Also used as data input 2 for FR Interface. Internal pulldown.
TRIG3 D6 I Trigger interface ball 3. Also used as data input 3 for FR Interface. Internal pulldown.
TRIG4 D5 I Trigger interface ball 4. Also used as chip select input for FR Interface. Internal pulldown.
TRIGCLK D4 I/O Trigger interface clock. Used as an input clock for FR Interface or output clock for trigger interface. Internal pulldown.
TXEN0 G3 I Pin control for muting DAC outputs or entering APP Sleep (see TX_EN_SEL). See also Transmit Enables. Internal pullup.
TXEN1 H3 I Pin control for muting DAC outputs or entering APP Sleep (see TX_EN_SEL). See also Transmit Enables. Internal pullup.
Analog functions
ATEST P9 O Analog test pin. Can be left disconnected if not used.
EXTREF K17 I/O Reference voltage output or input, determined by the EXTREF_EN register field. If the internal reference is used, the ball should be tied through 0.1uF to AGND.
RBIAS- H17 O Full-scale output current bias is set by the resistor tied from this terminal to RBIAS+.
RBIAS+ J17 O Full-scale output current bias is set by the resistor tied from this terminal to RBIAS-.
TDIODE+ P10 I Temperature diode positive terminal (to be sensed by an external circuit)
TDIODE- R10 I Temperature diode negative terminal (to be sensed by an external circuit)
TMSTPA+ A15 O Reserved.
TMSTPA- A16 O Reserved.
TMSTPB+ U15 O Reserved.
TMSTPB- U16 O Reserved.
Power Supplies
Note: one low ESL 0.1μF decoupling capacitor per power supply pin is recommended
VDDA18A G16, G17 I 1.8V supply voltage for DAC channel A. Can be combined with VDDA18B, but may degrade channel-to-channel crosstalk (XTALK).
VDDA18B L16, L17 I 1.8V supply voltage for DAC channel B. Can be combined with VDDA18A, but may degrade channel-to-channel crosstalk (XTALK).
VDDCLK08 J11, F12, H12, K12, M12, E13, G13, L13, N13 I 0.8V supply voltage for internal sampling clock distribution path. Noise or spurs on this supply may degrade phase noise performance. Recommended to separate from VDDDIG and VDDLA/B for best performance.
VDDCLK18 L14, M14 I 1.8V supply voltage for clock (CLK+/–) input buffer. Noise or spurs on this supply may degrade phase noise performance.
VDDCP18 J13, J14 I Data converter PLL 1.8V supply.
VDDDIG G4, J4, L4, F5, H5, K5, M5, N5, G6, J6, L6, H7, K7, G8, J8, L8, H9, K9 I 0.8V supply voltage for digital block. Recommended to separate from VDDLA/B and VDDCLK for best performance.
VDDEA F10, G10 I 0.8V supply voltage for channel A DAC encoder. Recommended to separate from VDDDIG for best performance. Can be combined with VDDEB.
VDDEB L10, M10 I 0.8V supply voltage for channel B DAC encoder. Recommended to separate from VDDDIG for best performance. Can be combined with VDDEA.
VDDIO C9, C10 I 1.8V supply for CMOS input and output terminals.
VDDLA F11, H11 I 0.8V supply for DAC analog latch for channel A. Separate from VDDLB for best channel-to-channel crosstalk (XTALK). Must be separated from VDDDIG for best performance.
VDDLB K11, M11 I 0.8V supply for DAC analog latch for channel B. Separate from VDDLA for best channel-to-channel crosstalk (XTALK). Must be separated from VDDDIG for best performance.
VDDR18 N4, P4 I 1.8V Supply voltage for SerDes receivers.
VDDSP18 J10 I Serdes PLL 1.8V supply.
VDDSYS18 F14, G14 I 1.8V supply voltage for SYSREF (SYSREF+/–) input buffer. Can be combined with VDDCLK18 when SYSREF is disabled during normal operation. This supply should be separate from VDDCLK18 when SYSREF is run continuously during operation to avoid noise and spur coupling and reduced phase noise performance.
VDDT C3, D3, L3, M3, N3, P3, R3, C4, R4, C5, R5, C6, R6, C7, F7, M7, R7, C8, F8, M8, R8, F9, M9 I 0.8V Supply voltage for SerDes termination.
VEEAM18 C12, D12, C13, D13, C14, D14 I –1.8V supply voltage for DAC current source bias for channel A. Can be combined with VEEBM18, but may degrade channel-to-channel crosstalk (XTALK).
VEEBM18 P12, R12, P13, R13, P14, R14 I –1.8V supply voltage for DAC current source bias for channel B. Can be combined with VEEAM18, but may degrade channel-to-channel crosstalk (XTALK).
VQPS P6, P7 I TI use only. Can be tied to DGND during normal operation.
Grounds
AGND A10, B10, D10, E10, N10, T10, U10, B11, C11, D11, P11, R11, T11, B12, A12, T12, U12, B13, T13, A14, B14, T14, U14, B15, C15, D15, P15, R15, T15, B16, H16, J16, K16, T16, A17, B17, T17, U17 - Analog ground.
DGND A1, B1, E1, H1, K1, N1, T1, U1, A2, B2, E2, H2, K2, N2, T2, U2 , A3, B3, T3, U3, F4, H4, K4, M4, G5, J5, L5, P5, A6, B6, E6, F6, H6, K6, M6, N6, T6, U6, E7, G7, J7, L7, N7, E8, H8, K8, N8 , P8, A9, B9, E9, G9, J9, L9, N9, R9, T9, U9, H10, K10 - Digital ground.
VSSCLK E11, G11, L11, N11, E12, G12, J12, L12, N12, F13, H13, K13, M13, E14, H14, K14, N14, E15, F15, G15, H15, J15, K15, L15, M15, N15, C16, D16, E16, F16, M16, N16, P16, R16, C17, F17, M17, R17 - Clock ground.