SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.8.6 JESD204C Interface Modes

The device JESD204C modes are configured with the parameters defined in Table 7-42, Table 7-43 and Table 7-44.

Table 7-42 JESD204C Interface Parameter Definitions
ParameterDescription
JMODEJESD204C mode number. The user configures this parameter to choose a supported mode. Most other parameters are derived from this setting. See Table 7-45.
LSLanes per sample stream. This is derived from JMODE. See Table 7-45.
LT

Ratio of input sample rate to clock. LT = FCLK / FS_IN. Note that DES2X mode does not affect the value of LT.

DSP_MODEn = Bypasss (all DSPs disabled, LT = 1.

Any DSP Enabled (and JESD_M > 0), LT is set by DSP_L

Any DSP Enabled (and JESD_M = 0), LT is not applicable

LxMaximum number of lanes used for a given JMODE. The link will scale down the number of active lanes (L) depending on how many channels are enabled. See JESD_M
MxMaximum number of streams for a given JMODE. Mx is computed automatically according to Table 7-45. The user can specify the actual number of streams (M) using the JESD_M register.
RNumber of bits transmitted per lane per DACCLK cycle. Derived from JMODE and LT (see Table 7-46). Based on R, the user must program REFDIV, MPY, and RATE registers. Additionally, the maximum DACCLK frequency is a function of R.
SISample Interleaving/Increment Factor. A value of 1 indicates that the standard transport layer mapping from the JESD204C standard is used (samples are mapped linearly from 0 to S-1). A value greater than 1 indicates that an alternate mapping is used as follows: Map samples starting with sample 0, incrementing the index by SI. Repeat this as many times as necessary to map all S samples, starting each repetition at an index that is one larger than the previous repetition. See JESD204C Format Diagrams.
KRFor 8b/10b operation, KR defines the legal values of K (frames per multiframe). The legal values are restricted to facilitate upset immunity of the elastic buffer. The multiframe length is restricted to a multiple of the elastic buffer depth of 128 characters (buffer depth is reduced to 32 or 64 characters if K*F is 32 or 64). Additionally, having less legal values for K minimizes verification burden. For 8b/10b modes, K is programmed via the KM1 register.
Table 7-43 JESD204C Link Parameters
ParameterDescriptionILAS Field NameValue for this device
see (1)
ADJCNTDAC LMFC adjustmentADJCNT[3:0]n/a
ADJDIRDAC LMFC adjustment directionADJDIR[0]n/a
BIDBank IDBID[3:0]n/a
CFNumber of control words per frameCF[4:0]0
CSNumber. of control bits per sampleCS[1:0]0
DIDDevice identification numberDID[7:0]n/a
FNumber of octets per frame (per lane)F[7:0]See Table 7-45
HDHigh Density FormatHD[0]See Table 7-45
JESDVJESD204 VersionJESDV[2:0]n/a
KNumber of frames per multiframeK[7:0]Set by KM1 register(2)
LNumber of lanes per linkL[4:0]ceiling(M/Mx*Lx)
LIDLane identification no.LID[4:0]n/a
MNumber of sample streams per link (see (1))M[7:0]Set by JESD_M register
NBits per sample (before adding control or tail bits)N[4:0]See Table 7-45
N'Total number of bits per sample (including control and tail bits)N’[4:0]See Table 7-45
PHADJPhase adjustment request to DACPHADJ[0]n/a
SNumber of samples per stream per frameS[4:0]See Table 7-45
SCRScrambling enabledSCR[0]Set by SCR register
SUBCLASSVDevice Subclass VersionSUBCLASSV[2:0]n/a
RES1Reserved field 1RES1[7:0]n/a
RES2Reserved field 2RES2[7:0]n/a
CHKSUMChecksum (sum of all above fields, modulo 256)FCHK[7:0]n/a
(1) In 8b and 10b modes, the transmitter may send link configuration octets during the ILAS. The values sent by the transmitter are not checked by this receiver, and they do not need to match the operational values of the receiver. For debugging purposes, specific ILAS octets can be captured and reported via SPI. See JCAP_PAGE and JCAP_OFFSET.
(2) In 8b/10b modes, K is controlled by the KM1 register. In 64b/66b modes, K = 256 x E/F (determined by JMODE).
Table 7-44 Link Parameters (applicable in 64b and 66b encoding only)
Parameter Description Value for this device
see (1)
E Number of multi-blocks per extended multi-block (64b and 66b encoding only) All modes use E=1, except when F=3, then E=3. (E is set automatically based on JMODE).

Each supported mode is assigned a mode number which can be programmed into the JMODE register with the parameters listed in Table 7-45.

Table 7-45 JESD Interface Modes
JMODEEncodingMax Input Sample Rate per Stream (GSPS)1, 2MAX Serdes Baud Rate (Gbps)R =

FBIT/ FDACCLK

3		NMx = Max # StreamsLs = Lanes/StreamLx = Max # LanesLT = InterpolationJESD FormatKR
MINMAXFSHDSI
08b/10b2227.51.251611616112160132, 64, 128
64b/66b2222.691.03125
18b/10b1332.52.5/LT16281618280132, 64, 128
64b/66b15.7632.52.0625/LT
28b/10b6.532.55/LT164416116240132, 64, 128
64b/66b7.8832.54.125/LT
38b/10b3.2532.510/LT168216432220132, 64, 128
64b/66b3.9432.58.25/LT
48b/10b1.62532.520/LT16818464210132, 64, 128
64b/66b1.9732.516.5/LT
58b/10b0.8132.540/LT168½48128410116,32,64
64b/66b0.9832.533/LT
68b/10b0.4132.580/LT168¼21625681018,16,32
64b/66b0.4932.566/LT
78b/10b0.232.5160/LT168 â…›132256161014,8,16
64b/66b0.2532.5132/LT
88b/10b222211211616118800168,16,32
64b/66b2218.150.825
98b/10b2227.51.251211212112161132,64, 128
64b/66b2222.691.03125
108b/10b17.3332.5212281611840088,16,32
64b/66b21.0132.51.65
118b/10b1332.52.512261211281132,64, 128
64b/66b15.7632.52.0625
128b/10b8.6732.541224811820048,16,32
64b/66b10.5132.53.3
138b/10b6.532.551223611241132,64, 128
64b/66b7.8832.54.125
148b/10b2213.750.625811616111160164, 128,256
64b/66b2211.340.5156
158b/10b2227.51.258281611180164, 128,256
64b/66b2222.691.03125
168b/10b1332.52.5824811140164, 128,256
64b/66b15.7632.52.0625
178b/10b4n/an/an/a1228161131601n/a
64b/66b21.0132.51.546875
  1. At minimum interpolation rate
  2. The encoding (8b/10b or 64b/66b) is restricted for certain combinations of JMODE and LT. See Table 7-46 for details.
  3. See Table 7-47 (8b/10b) or Table 7-48 (64b/66b) to program the PHY PLL based on the value of R.
  4. This mode does not support 8b/10b encoding.
Table 7-46 Interpolation/Upsampling Factors (LT) supported vs. JMODE
User Specified Parameters Derived Parameters
JMODE LT R1 (JENC=0)

(8b/10b)

 R2 (JENC=1)

(64b/66b)
0 1 1.25 1.03125
1 1 2.5 2.0625
4 0.625 0.515625
6 0.41667 -
8 0.3125 -
2 1 5 4.125
4 1.25 1.03125
6 0.833 0.6875
8 0.625 0.515625
12 0.41667 -
16 0.3125 -
3 4 2.5 2.0625
6 1.667 1.375
8 1.25 1.03125
12 0.833 0.6875
16 0.625 0.515625
24 0.41667 -
32 0.3125 -
4 4 5 4.125
6 3.333 2.75
8 2.5 2.0625
12 1.667 1.375
16 1.25 1.03125
24 0.833 0.6875
32 0.625 0.515625
48 0.41667 -
64 0.3125 -
5 8 5 4.125
12 3.333 2.75
16 2.5 2.0625
24 1.667 1.375
32 1.25 1.03125
48 0.833 0.6875
64 0.625 0.515625
96 0.41667 -
128 0.3125 -
6 16 5 4.125
24 3.333 2.75
32 2.5 2.0625
48 1.667 1.375
64 1.25 1.03125
96 0.833 0.6875
128 0.625 0.515625
192 0.41667 -
256 0.3125 -
7 32 5 4.125
48 3.333 2.75
64 2.5 2.0625
96 1.667 1.375
128 1.25 1.03125
192 0.833 0.6875
256 0.625 0.515625
8 1 1 0.825
9 1 1.25 1.031255
10 125 2 1.65
11 1 2.5 2.0625
12 1 4 3.3
13 1 5 4.125
14 1 0.625 0.515625
15 1 1.25 1.03125
16 1 2.5 2.0625
17 1 - 1.546875
  1. See Table 7-47 (8b/10b) or Table 7-48 (64b/66b) to program the PHY PLL based on the value of R.
  2. If the value of R is unspecified, the associated lane encoding (8b/10b or 64b/66b) is not supported for that particular JMODE and LT settings.
Table 7-47 Parameters derived from R Parameter for 8b/10b Modes (JENC = 0)
R Parameter Maximum DAC Clock Rate (FDACCLK) Maximum Lane Rate

(FBIT = R x FDACCLK)
0.3125 (40/128) 25.6GHz 8Gbps
0.416667 (40/96) 25.6GHz 10.667Gbps
0.625 (40/64) 25.6GHz 16Gbps
0.833333 (40/48) 19.2GHz 16Gbps
1 (40/40) 16GHz 16Gbps
1.25 (40/32) 12.8GHz 16Gbps
1.666667 (40/24) 9.6GHz 16Gbps
2 (40/20) 8GHz 16Gbps
2.5 (40/16) 6.4GHz 16Gbps
3.333333 (40/12) 4.8GHz 16Gbps
4 (40/10) 4GHz 16Gbps
5 (40/8) 3.2GHz 16Gbps
Table 7-48 Parameters derived from R Parameter for 64b/66b Modes (JENC = 0)
R Parameter Maximum DAC Clock Rate (FDACCLK) Maximum Lane

Rate (FBIT = R x FDACCLK)
0.515625 (33/64) 25.6GHz 13.2Gbps
0.6875 (33/48) 25.6GHz 17.6Gbps
0.825 (33/40) 25.6GHz 21.12Gbps
1.03125 (33/32) 25.6GHz 26.4Gbps
1.375 (33/24) 23.636GHz 32.5Gbps
1.546875 (99/64) 21.010GHz 32.5Gbps
1.65 (33/20) 19.697GHz 32.5Gbps
2.0625 (33/16) 15.758GHz 32.5Gbps
2.75 (33/12) 11.818GHz 32.5Gbps
3.3 (33/10) 9.848GHz 32.5Gbps
4.125 (33/8) 7.87GHz 32.5Gbps