SBASAO8 June 2025 DAC39RF20
ADVANCE INFORMATION
The clock recovery algorithms operate to adjust the clocks used to sample nSRX+ and nSRX- so that the data samples are taken midway between data transitions.
The algorithm uses a basic technique to determine whether the sampling clock is correctly placed, and if not whether the sampling clock needs to be moved earlier or later. When two contiguous data samples are different, the edge sample between the two is examined. The sampling clock can be considered early or late depending on whether the edge sample matches the first or second data sample respectively.
Every 32 UI, 32 such comparisons are made, with each result counted as a vote to move the sample point either earlier or later (positions where no transition occurred produce no vote). If the majority are early or late votes, an internal counter is incremented or decremented respectively. When the internal counter overflows or underflows, the sampling instant of the clock is adjusted later or earlier respectively (by 1/64 UI).
Each time the sampling instant of the clock is adjusted, the internal counter returns to mid-code, and a blanking interval occurs (also called “settling time”). During the blanking interval, no votes are counted. This is necessary to make sure that the incoming data and edge samples have reflected the new sampling instant. This can prevent the algorithm from overshooting. The blanking interval (settling time) is defined by the CDRSTL register field. The largest setting can provide power savings.
The size of the internal counter (and therefore the number of increments or decrements required to adjust the sampling instant) is programmable (see CRDVOTE register field).
Note that the clock recovery algorithm continues to operate even if the SIG_DET[n] status bit is low (loss of signal).