SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.6.7 NCO Square Wave Mode

The NCO inside each DSP channel can be configured to produce a square waveform instead of sine/cosine waveforms. This feature is designed for systems that want to synthesize a clock signal using the DAC with programmable frequency, phase, amplitude, slew time and duty cycle. Enable this feature on DSPn by setting NCO_SQ_MODE[n]. This mode is compatible with all the DDS modes, but is not supported for DUC mode (see the DSP_MODEn). The DDS-SPI mode is the primary use case for this feature. But if frequency ramping is necessary, DDS-Vector mode or DDS-Streaming mode can be useful.

The slew time and duty cycle are adjustable using the SLEW and DUTY_CYCLE registers. The slew time is programmed as a proportion of the period, so when the NCO frequency is changed, the period; therefore, the slew time also changes.

The frequency, phase, and amplitude are controlled in the same fashion as if the NCO was producing sine/cosine waveforms. This is summarized in Table 7-25.

Table 7-25 NCO Parameter Control Method vs DSP Mode
NCO Parameter Control Method for the NCO Parameter depends on DSP mode
DDS SPI Mode DDS Streaming Mode DDS Vector Mode
Frequency FREQ register Depends on STREAM_MODE Vector Engine
Phase PHASE register Depends on STREAM_MODE Vector Engine
Amplitude AMP register Depends on STREAM_MODE Vector Engine
Slew SLEW register SLEW register SLEW register
Duty Cycle DUTY_CYCLE register DUTY_CYCLE register DUTY_CYCLE register

The square waveform produced by the NCO is depicted in Figure 7-43.

DAC39RF20 NCO Square Waveform Properties Figure 7-43 NCO Square Waveform Properties

The duty cycle is adjustable over a wide range, but the user must never adjust the duty cycle to extreme values that cause the falling edge of the signal to “collide” with the rising edge. The supported duty cycle range depends on the SLEW setting and is listed in Table 7-26.

Table 7-26 Supported Duty Cycle Range vs Slew Time
SLEW Setting Slew time as a percentage of the period (25% * 2-SLEW) Acceptable duty cycle range [percent] Supported range of DUTY_CYCLE register (decimal)
0 25% 25% - 75% 1024 to 3072
1 12.5% 12.5% - 87.5% 512 to 3584
2 6.25% 6.25% - 93.75% 256 to 3840
3 3.125% 3.125% - 96.875% 128 to 3968
4 1.5625% 1.5625% - 98.4375% 64 to 4032
5 0.78125% 0.78125% - 99.21875% 32 to 4064
6 0.390625% 0.390625% - 99.60938% 16 to 4080
7 0.195313% 0.195313% - 99.80469% 8 to 4088
8 0.097656% 0.097656% - 99.90234% 4 to 4092
9 0.048828% 0.048828% - 99.95117% 2 to 4094

Notes about the square wave generator:

  1. Square wave mode only makes sense to use in NRZ or DES2XL DAC output modes (1st Nyquist modes) and with a frequency < 1/10th the DAC clock rate, otherwise there are not enough data points during the cycle to define the transition periods.
  2. The SLEW and DUTY_CYCLE parameters can be changed while the NCO is producing an output, but the parameters do not go into effect until the DSP receives a trigger event. Updating these parameters in this way is not clean as the waveform can glitch to the new waveform. To prevent glitches, the waveform can be gated low to update the SLEW and DUTY_CYCLE parameters using NCO_SQ_EN.
  3. When using the square waveform with DDS Vector mode, use the DDS_HOLD feature so that the vector engine holds on a vector and keeps producing a waveform when waiting for a trigger. If you do not use this mode, the output mutes by going to mid-code and does not gate the square wave into the low state.
  4. Internally, the square wave swings from -32768 to +32767 and then is scaled by the mixer. When the DDS amplitude (AMP) is full scale (32767), this scales the waveform down slightly, so the output swings from 32767 to +32766.
  5. Setting the DDS amplituide to 0 is not the same as gating the waveform. Setting the amplitude to 0 causes the swing to be 0 at mid-code. Gating the waveform low keeps the waveform at the “logic low” or “minimum level” (for example -32767 if the DDS amplitude is set to 32767).
  6. The square wave mode is not compatible with DSP_FORMAT=1.
  7. In square wave mode, do not set the NCO frequency higher than FDAC/4.
  8. The user must take care that the SLEW setting is not too high. If the setting is too high, the NCO can fail to produce output samples during the transition period. As a result, the jitter of the resulting signal can be poor as every edge is rounded off to the nearest sampling period. Better jitter performance occurs when the the slew time consists of multiple sample periods. The number of sample periods in the slew time is equal to 0.25 * 2-SLEW[n] * 264 / FREQ[n] (assuming DDS SPI mode). A low-pass anti-imaging filter on the DAC output can help smooth out the transitions to produce a smoother clock signal.
  9. DES2XL mode is advantageous to use as DES2XL increases the number of points in the transition period. However, as the DES2x digital filter limits the digital bandwidth, the filter produces ripple near the transition period that is larger than the square wave amplitude. Therefore, the square wave amplitude must be backed off by 2-3% to prevent saturating the digital signal.
  10. See Bandwidth Optimization for Square Wave Mode on optimization of the DAC output bandwidth for square wave mode.