SBASAO8 Data sheet

SBASAO8 June 2025 DAC39RF20

ADVANCE INFORMATION

6.9 Switching Characteristics

Typical values at T_A = +25°C, minimum and maximum values over operating free-air temperature range, typical supply voltages, f_CLK = 16GHz, external clock mode, I_{FS_SWITCH} = 41mA, single tone amplitude = 0dBFS, Dither and DEM enabled, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
JESD204C SERDES INTERFACE [15:0]SRX-/+
f_SERDESMAX	SERDES bit rate maximum		32.5			Gbps
f_SERDESMIN	SERDES bit rate minimum				1.5	Gbps
f_REFMAX	Serdes PLL reference frequency maximum		2040			MHz
f_REFMIN	Serdes PLL reference frequency minimum				82	MHz
f_VCOMAX	Serdes PLL frequency maximum		16.25			GHz
f_VCOMIN	Serdes PLL Frequency minimum				8.125	GHz
SJ_LF	Low frequency sinusoidal jitter tolerance	20kHz			5	UI
SJ_HF	High frequency sinusoidal jitter tolerance	20MHz			0.05	UI
BHPUJ	Bounded high-probability uncorrelated jitter tolerance				0.25	UI
BHPCJ	Bounded high-probability correlated jitter tolerance				0.2	UI
TUJ	Total jitter tolerance⁽²⁾				0.7	UI
BOOST_CTLE	CTLE Boost at data rate Nyquist frequency with respect to DC		9			dB
R_LDIFF	Differential return loss	f_IN = 0.275 - 0.75*f_SERDES			-9.7	dB
LATENCY
T_DACCLK	DAC clock period			1 / f_CLK
t_PD(RX)	Serdes RX analog propagation delay	Serdes RX analog propagation delay		250		ps
t_PDI	Input clock rising edge cross-over to output sample cross-over	Input clock rising edge cross-over to output sample cross-over		250		ps
t_{DAC_LAT}	Digital path latency from SYSREF rising edge to DAC output		See XLS Calculator
t_RELEASE	Latency from SYSREF rising edge to elastic buffer release		See XLS Calculator
t_RXIN	Latency from SERDES Input to elastic buffer release		See XLS Calculator
SERIAL PROGRAMMING INTERFACE
f_{S_C}	serial clock frequency				15	MHz
t_P	serial clock period		33			ns
t_PH	serial clock pulse width high		16			ns
t_PL	serial clock pulse width low		16			ns
t_SU	SDI setup		8			ns
t_H	SDI hold		1.5			ns
t_IZ	SDI TRI-STATE				3	ns
t_ODZ	SDO driven to TRI-STATE	200fF load	0		6	ns
t_OZD	SDO TRI-STATE to driven	200fF load	0		6	ns
t_OD	SDO output delay	200fF load	0		6	ns
t_CSS	SCS setup		8			ns
t_CSH	SCS hold		1.5			ns
t_IAG	Inter-access gap		16			ns
t_CRS	SCS setup to RESET	RESET rising edge	0			ns
t_CSH	SCS hold to RESET	RESET rising edge	30			ns
FAST RECONFIGURATION (FR) AND TRIGGER INTERFACE
F_TRIGCLK	FRCLK frequency				200	MHz
t_{TRIGCLK_P}	FRCLK period		5			ns
t_{TRIGCLK_PH}	FRCLK pulse width high		2.4			ns
t_FRCLK_{_PL}	FRCLK pulse width low		2.4			ns
t_{TRIG0_3_SU}	TRIG[3:0] setup	relative to TRIGCLK output rising edge⁽³⁾	2.6			ns
t_{TRIG0_3}_{_H}	TRIG[3:0] hold	relative to TRIGCLK output rising edge⁽³⁾	0.5			ns
t_{TRIG4_SU}	TRIG4 setup	relative to TRIGCLK output rising edge⁽³⁾	2.5			ns
t_{TRIG4_H}	TRIG4 hold	relative to TRIGCLK output rising edge⁽³⁾	0.6			ns
t_{FR_IAG}	Inter-access gap		5			ns
t_{FR_PFIRWAIT}	Wait time after setting FR_PFIR_PROG = 1		1024			DACCLKs
PLL/VCO Characteristics
f_REF	Reference clock frequency		0.1		3	GHz
f_DACCLK	DAC sample clock with converter PLL/VCO		8.125		17	GHz
PLL_RATIO	Ratio of reference clock to VCO frequency⁽⁴⁾		6		255
PLL_DIV	Ratio of VCO frequency to DAC sample clock		1		1
PN_PLL	PLL/VCO Phase Noise, f_REF = 2GHz⁽¹⁾	f_VCO = 16GHz, 100Hz offset		-102		dBc/Hz
		f_VCO = 16GHz, 1KHz offset		-112		dBc/Hz
		f_VCO = 16GHz, 10kHz offset		-122		dBc/Hz
		f_VCO = 16GHz, 100kHz offset		-129		dBc/Hz
		f_VCO = 16GHz, 1MHz offset		-132		dBc/Hz
		f_VCO = 16GHz, 10MHz offset		-130		dBc/Hz
		f_VCO = 16GHz, 100MHz offset		-139		dBc/Hz
PN_PLLINT	1kHz to 100MHz, f_REF = 2GHz⁽¹⁾	f_VCO = 20GHz		-55		dBc

(1) Measured at DAC output at 1GHz, normalized to VCO frequency.

(2) Includes high-frequency sinusoidal jitter; the Gaussian jitter (GJ) portion is defined with respect to a BER of 10⁻¹⁵.

(3) with 4pF load on TRIGCLK

(4) Device supports 2^N*3^M, where N = 1 - 16 and M = 0 or 1