SBASAO8 June   2025 DAC39RF20

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI Interface Timing Diagrams
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RF Mode
        3. 7.3.1.3 DES Modes
      2. 7.3.2  DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3  DEM and Dither
      4. 7.3.4  Offset Adjustment
      5. 7.3.5  Clocking Subsystem
        1. 7.3.5.1 Converter Phase Locked Loop (CPLL)
        2. 7.3.5.2 Clock and SYSREF Delay
        3. 7.3.5.3 SYSREF Capture and Monitoring
          1. 7.3.5.3.1 SYSREF Frequency Requirements
          2. 7.3.5.3.2 SYSREF Pulses for Full Alignment
          3. 7.3.5.3.3 Automatic SYSREF Calibration and Tracking
            1. 7.3.5.3.3.1 SYSREF Automatic Calibration Procedure
            2. 7.3.5.3.3.2 Multi-device Alignment
            3. 7.3.5.3.3.3 Calibration Failure
            4. 7.3.5.3.3.4 SYSREF Tracking
        4. 7.3.5.4 Trigger Clocking
      6. 7.3.6  Digital Signal Processing Blocks
        1. 7.3.6.1  Bypass Mode
        2. 7.3.6.2  DUC Mode
          1. 7.3.6.2.1 Digital Upconverter (DUC)
            1. 7.3.6.2.1.1 Interpolation Filters
            2. 7.3.6.2.1.2 Numerically Controlled Oscillator (NCO)
              1. 7.3.6.2.1.2.1 Phase-continuous NCO Update Mode
              2. 7.3.6.2.1.2.2 Phase-coherent NCO Update Mode
              3. 7.3.6.2.1.2.3 Phase-sync NCO Update Mode
              4. 7.3.6.2.1.2.4 NCO Synchronization
                1. 7.3.6.2.1.2.4.1 JESD204C LSB Synchronization
        3. 7.3.6.3  DDS SPI Mode
        4. 7.3.6.4  DDS Vector Mode
          1. 7.3.6.4.1 Second Order Amplitude Support
          2. 7.3.6.4.2 Vector Order and Symmetric Vector Mode
          3. 7.3.6.4.3 Initial Startup
          4. 7.3.6.4.4 Trigger Queuing
          5. 7.3.6.4.5 Trigger Burst
          6. 7.3.6.4.6 Hold Mode
          7. 7.3.6.4.7 Indexing Mode
          8. 7.3.6.4.8 Queued or Burst Triggers in Indexing-Mode
          9. 7.3.6.4.9 Writing Vectors While DDS is Enabled
        5. 7.3.6.5  DDS Streaming Mode
        6. 7.3.6.6  DSP Triggering
          1. 7.3.6.6.1 Trigger Latency
        7. 7.3.6.7  NCO Square Wave Mode
          1. 7.3.6.7.1 Square Wave Enable
        8. 7.3.6.8  DSP Mute Function
        9. 7.3.6.9  DSP Output Gain
        10. 7.3.6.10 Complex Output Support
        11. 7.3.6.11 Channel Bonder
        12. 7.3.6.12 Programmable FIR Filter
          1. 7.3.6.12.1 PFIR Coefficients
          2. 7.3.6.12.2 PFIR Reflection Cancellation Mode
          3. 7.3.6.12.3 PFIR Power Savings
          4. 7.3.6.12.4 PFIR Usage
        13. 7.3.6.13 DES Interpolator
          1. 7.3.6.13.1 DAC Mute Function
      7. 7.3.7  Serdes Physical Layer
        1. 7.3.7.1 Serdes PLL
          1. 7.3.7.1.1 Enabling the Serdes PLL
          2. 7.3.7.1.2 Reference Clock
          3. 7.3.7.1.3 PLL VCO Calibration
          4. 7.3.7.1.4 Serdes PLL Loop Bandwidth
        2. 7.3.7.2 Serdes Receiver
          1. 7.3.7.2.1 Serdes Data Rate Selection
          2. 7.3.7.2.2 Serdes Receiver Termination
          3. 7.3.7.2.3 Serdes Receiver Polarity
          4. 7.3.7.2.4 Serdes Clock Data Recovery
          5. 7.3.7.2.5 Serdes Equalizer
            1. 7.3.7.2.5.1 Adaptive Equalization
            2. 7.3.7.2.5.2 Fixed Equalization
            3. 7.3.7.2.5.3 Pre and Post Cursor Analysis
          6. 7.3.7.2.6 Serdes Receiver Eyescan
            1. 7.3.7.2.6.1 Eyescan Procedure
            2. 7.3.7.2.6.2 Building an Eye Diagram
        3. 7.3.7.3 Serdes PHY Status
      8. 7.3.8  JESD204C Interface
        1. 7.3.8.1 Deviation from JESD204C Standard
        2. 7.3.8.2 Link Layer
          1. 7.3.8.2.1 Serdes Crossbar
          2. 7.3.8.2.2 Bit Error Rate Tester
          3. 7.3.8.2.3 Scrambler and Descrambler
          4. 7.3.8.2.4 64b and 66b Decoding Link Layer
            1. 7.3.8.2.4.1 Sync Header Alignment
            2. 7.3.8.2.4.2 Extended Multiblock Alignment
            3. 7.3.8.2.4.3 Data Integrity
          5. 7.3.8.2.5 8B and 10B Encoding Link Layer
            1. 7.3.8.2.5.1 Code Group Synchronization (CGS)
            2. 7.3.8.2.5.2 Initial Lane Alignment Sequence (ILAS)
            3. 7.3.8.2.5.3 Multi-frames and the Local Multiframe Clock (LMFC)
            4. 7.3.8.2.5.4 Frame and Multiframe Monitoring
            5. 7.3.8.2.5.5 Link Restart
            6. 7.3.8.2.5.6 Link Error Reports
            7. 7.3.8.2.5.7 Watchdog Timer (JTIMER)
        3. 7.3.8.3 SYSREF Alignment Required in Subclass 1 Mode
        4. 7.3.8.4 Transport Layer
        5. 7.3.8.5 JESD204C Debug Capture (JCAP)
          1. 7.3.8.5.1 Physical Layer Debug Capture
          2. 7.3.8.5.2 Link Layer Debug Capture
          3. 7.3.8.5.3 Transport Layer Debug Capture
        6. 7.3.8.6 JESD204C Interface Modes
          1. 7.3.8.6.1 JESD204C Format Diagrams
            1. 7.3.8.6.1.1 16-bit Formats
            2. 7.3.8.6.1.2 12-bit Formats
            3. 7.3.8.6.1.3 8-bit Formats
          2. 7.3.8.6.2 DUC and DDS Modes
      9. 7.3.9  Data Path Latency
      10. 7.3.10 Multi-Device Synchronization and Deterministic Latency
        1. 7.3.10.1 Programming RBD
        2. 7.3.10.2 Multiframe Lengths less than 32 Octa-Bytes (256 Bytes)
        3. 7.3.10.3 Recommended Algorithm to Determine the RBD Value
        4. 7.3.10.4 Operation in Subclass 0 Systems
      11. 7.3.11 Link Reset
      12. 7.3.12 Alarm Generation
        1. 7.3.12.1 Over Range Detection
        2. 7.3.12.2 Over Range Masking
      13. 7.3.13 Mute Function
        1. 7.3.13.1 Alarm Data Path Muting
        2. 7.3.13.2 Transmit Enables
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Modes
  9. 8 Programming
    1. 8.1 Using the Standard SPI Interface
      1. 8.1.1 SCS
      2. 8.1.2 SCLK
      3. 8.1.3 SDI
      4. 8.1.4 SDO
      5. 8.1.5 Serial Interface Protocol
      6. 8.1.6 Streaming Mode
    2. 8.2 Using the Fast Reconfiguration Interface
    3. 8.3 Register Maps
      1. 8.3.1  Standard_SPI-3.1 Registers
      2. 8.3.2  System Registers
      3. 8.3.3  Trigger Registers
      4. 8.3.4  CPLL_AND_CLOCK Registers
      5. 8.3.5  SYSREF Registers
      6. 8.3.6  JESD204C Registers
      7. 8.3.7  JESD204C_Advanced Registers
      8. 8.3.8  SerDes_Equalizer Registers
      9. 8.3.9  SerDes_Eye-Scan Registers
      10. 8.3.10 SerDes_Lane_Status Registers
      11. 8.3.11 SerDes_PLL Registers
      12. 8.3.12 DAC_and_Analog_Configuration Registers
      13. 8.3.13 Datapath Registers
      14. 8.3.14 NCO_and_Mixer Registers
      15. 8.3.15 Alarm Registers
      16. 8.3.16 Fuse_Control Registers
      17. 8.3.17 Fuse_Backed Registers
      18. 8.3.18 DDS_Vector_Mode Registers
      19. 8.3.19 Programmable_FIR Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Startup Procedure
      2. 9.1.2 Bandwidth Optimization for Square Wave Mode
    2. 9.2 Typical Application: Ku-Band Radar Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power Up and Down Sequence
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines and Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.6 Electrical Characteristics - AC Specifications

Typical values at TA = +25°C, minimum and maximum values over operating junction temperature range, typical supply voltages, fCLK = 22GHz (external clock mode), IFS_SWITCH = 20mA, single tone amplitude = -0.1dBFS, Dither and DEM enabled, 64b/66b encoding, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MODE INDEPENDENT PARAMETERS
fDACCLK DAC clock rate
= fSAMPLE in NRZ and RF mode
= fSAMPLE/2 in DES2XL/H modes		 22 GHz
BW Analog output bandwidth (–3dB) Excluding sinx/x response. Useable frequency range may exceed the –3 dB point. 18 GHz
Crosstalk Isolation between channel A (DACOUTA+/–) and channel B (DACOUTB+/-), fOUT = -25MHz offset on victim channel, dual channel device only fOUT = 97MHz, NRZ mode 90 dBc
fOUT = 2897MHz, NRZ mode 75 dBc
fOUT = 5897MHz, NRZ mode 70 dBc
fOUT = 8897MHz, NRZ mode 66 dBc
fOUT = 13103MHz, RF mode 60 dBc
fOUT = 16103MHz, RF mode 55 dBc
fOUT = 19103MHz, RF mode 50 dBc
DAC OUTPUT TIME DOMAIN CHARACTERISTICS
tRISE 10% to 90%(1) JMODE 0, 1x Interpolation 18 ps
tFALL 90% to 10%(1) JMODE 0, 1x Interpolation 18 ps
fCLK fixed spur Relative to fullscale sinewave at 1 GHz NRZ Mode, fOUT = DC (mid-code), DEM/Dither off 50 dBc
NRZ Mode, fOUT = DC (mid-code), DEM/Dither on 50 dBc
DES2XL Mode, fOUT = DC (mid-code), DEM/Dither off 50 dBc
DES2XL Mode, fOUT = DC (mid-code), DEM/Dither on 50 dBc
2*fCLK fixed spur Relative to fullscale sinewave at 1 GHz DES2XL Mode, fOUT = DC (mid-code), DEM/Dither off 50 dBc
DES2XL Mode, fOUT = DC (mid-code), DEM/Dither on 50 dBc
22GSPS GSPS, JMODE 2, 4x Int, NRZ MODE
POUT Output power into 100Ω load(2) fOUT = 97MHz 1.0 dBm
fOUT = 2897MHz 0.6 dBm
fOUT = 2897MHz, IFS_SWITCH = 40mA 6.6 dBm
fOUT = 5897MHz -0.5 dBm
fOUT = 8897MHz -3.5 dBm
fOUT = 8897MHz, IFS_SWITCH = 40mA 2.5 dBm
SFDR Spurious free dynamic range (SFDR) across 0 - FDACCLK/2 fOUT = 97MHz –74 dBc
fOUT = 2897MHz -56 dBc
fOUT = 2897MHz, IFS_SWITCH = 40mA -53 dBc
fOUT = 5897MHz -44 dBc
fOUT = 8897MHz -36 dBc
fOUT = 8897MHz, IFS_SWITCH = 40mA -45 dBc
HD2 Second harmonic (HD2), 0 - FDACCLK/2 fOUT = 97MHz –81 dBc
fOUT = 2897MHz -56 dBc
fOUT = 2897MHz, IFS_SWITCH = 40mA -55 dBc
fOUT = 5897MHz -44 dBc
fOUT = 8897MHz -36 dBc
fOUT = 8897MHz, IFS_SWITCH = 40mA -38 dBc
HD3 Third harmonic (HD3), 0 - FDACCLK/2 fOUT = 97MHz –74 dBc
fOUT = 2897MHz -75 dBc
fOUT = 2897MHz, IFS_SWITCH = 40mA -60 dBc
fOUT = 5897MHz -70 dBc
fOUT = 8897MHz -54 dBc
fOUT = 8897MHz, IFS_SWITCH = 40mA -60 dBc
SFDRNONHD23 non-HD2/3 SFDR, 0 - FDACCLK/2 fOUT = 97MHz –98 dBc
fOUT = 2897MHz –94 dBc
fOUT = 2897MHz, IFS_SWITCH = 40mA –94 dBc
fOUT = 5897MHz –71 dBc
fOUT = 8897MHz –74 dBc
fOUT = 8897MHz, IFS_SWITCH = 40mA –74 dBc
IMD3 Third-order two tone intermodulation distortion fOUT = 97 +/- 10MHz, -7dBFS/tone –80 dBc
fOUT = 2897 +/- 10MHz, -7dBFS/tone -75 dBc
fOUT = 2897 +/- 10MHz, -7dBFS/tone, IFS_SWITCH = 40mA -65 dBc
fOUT = 5897 +/- 10MHz, -7dBFS/tone -75 dBc
fOUT = 8897 +/- 10MHz, -7dBFS/tone -65 dBc
fOUT = 8897 +/- 10MHz, -7dBFS/tone, IFS_SWITCH = 40mA -70 dBc
NSD Noise spectral density, large signal, sinusoidal output, DEM/Dither on fOUT = 97MHz, 70MHz offset from fOUT –160 dBc/Hz
fOUT = 2897MHz, 70MHz offset from fOUT –158 dBc/Hz
v= 2897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –158 dBc/Hz
fOUT = 5897MHz, 70MHz offset from fOUT –156 dBc/Hz
fOUT = 8897MHz, 70MHz offset from fOUT –152 dBc/Hz
fOUT = 8897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –152 dBc/Hz
NSD Noise spectral density, large signal, sinusoidal output, DEM/Dither disabled fOUT = 97MHz, 70MHz offset from fOUT –170 dBc/Hz
fOUT = 2897MHz, 70MHz offset from fOUT –168 dBc/Hz
fOUT = 2897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –168 dBc/Hz
fOUT = 5897MHz, 70MHz offset from fOUT –166 dBc/Hz
fOUT = 8897MHz, 70MHz offset from fOUT –160 dBc/Hz
fOUT = 8897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –160 dBc/Hz
NSD Noise spectral density, small signal, sinusoidal output, DEM/Dither on AOUT = -20 dBFS, fOUT = 97MHz, 70MHz offset from fOUT –163 dBFS/Hz
AOUT = -20dBFS, fOUT = 2897MHz, 70MHz offset from fOUT –162 dBFS/Hz
AOUT = -20dBFS, fOUT = 2897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –162 dBFS/Hz
AOUT = -20dBFS, fOUT = 5897MHz, 70MHz offset from fOUT –160 dBFS/Hz
AOUT = -20dBFS, fOUT = 8897MHz, 70MHz offset from fOUT –160 dBFS/Hz
AOUT = -20dBFS, fOUT = 8897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –160 dBFS/Hz
NSD Noise spectral density, small signal, sinusoidal output, DEM/Dither disabled AOUT = -20dBFS, fOUT = 97MHz, 70MHz offset from fOUT –170 dBFS/Hz
AOUT = -20dBFS, fOUT = 2897MHz, 70MHz offset from fOUT –169 dBFS/Hz
AOUT = -20dBFS, fOUT = 2897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –169 dBFS/Hz
AOUT = -20dBFS, fOUT = 5897MHz, 70MHz offset from fOUT –168 dBFS/Hz
AOUT = -20dBFS, fOUT = 8897MHz, 70MHz offset from fOUT –167 dBFS/Hz
AOUT = -20dBFS, fOUT = 8897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –167 dBFS/Hz
NPR Noise power ratio, peak Signal spanning C-Band, 200MHz notch in center, IFS_SWITCH = 40mA 53 dBc
ENOB Effective number of bits Calculated from peak NPR, IFS_SWITCH = 40mA 8.5 bits
PN Additive DAC phase noise, external clock contribution subtracted out fOUT = 10GHz, 100Hz offset dBc/Hz
fOUT = 10GHz, 1kHz offset -120 dBc/Hz
fOUT = 10GHz, 10kHz offset -132 dBc/Hz
fOUT = 10GHz, 100kHz offset -140 dBc/Hz
fOUT = 10GHz, 1MHz offset -142 dBc/Hz
fOUT = 10GHz, 10MHz offset -143 dBc/Hz
PN Additive DAC phase noise, external clock contribution subtracted out, DEM/Dither disabled fOUT = 10GHz, 100Hz offset dBc/Hz
fOUT = 10GHz, 1kHz offset -120 dBc/Hz
fOUT = 10GHz, 10kHz offset -132 dBc/Hz
fOUT = 10GHz, 100kHz offset -140 dBc/Hz
fOUT = 10GHz, 1MHz offset -147 dBc/Hz
fOUT = 10GHz, 10MHz offset -149 dBc/Hz
22GSPS GSPS, JMODE 2, 4x Int, DES2xL MODE
POUT Output power into 100Ω load(2) fOUT = 97MHz 1.0 dBm
fOUT = 2897MHz 0.8 dBm
fOUT = 2897MHz, IFS_SWITCH = 40mA 6.8 dBm
fOUT = 5897MHz 0.4 dBm
fOUT = 8897MHz -1.5 dBm
fOUT = 8897MHz, IFS_SWITCH = 40mA 4.5 dBm
SFDR Spurious free dynamic range (SFDR) across 0 - FDACCLK/2 fOUT = 97MHz -58 dBc
fOUT = 2897MHz -59 dBc
fOUT = 2897MHz, IFS_SWITCH = 40mA -76 dBc
fOUT = 5897MHz -66 dBc
fOUT = 8897MHz -66 dBc
fOUT = 8897MHz, IFS_SWITCH = 40mA -60 dBc
HD2 Second harmonic (HD2), 0 - FDACCLK/2 fOUT = 97MHz –80 dBc
fOUT = 2897MHz -58 dBc
fOUT = 2897MHz, IFS_SWITCH = 40mA -59 dBc
fOUT = 5897MHz -76 dBc
fOUT = 8897MHz -66 dBc
fOUT = 8897MHz, IFS_SWITCH = 40mA -66 dBc
HD3 Third harmonic (HD3), 0 - FDACCLK/2 fOUT = 97MHz –74 dBc
fOUT = 2897MHz -71 dBc
fOUT = 2897MHz, IFS_SWITCH = 40mA -60 dBc
fOUT = 5897MHz -80 dBc
fOUT = 8897MHz -71 dBc
fOUT = 8897MHz, IFS_SWITCH = 40mA -80 dBc
SFDRNONHD23 non-HD2/3 SFDR, 0 - FDACCLK/2 fOUT = 97MHz –92 dBc
fOUT = 2897MHz –87 dBc
fOUT = 2897MHz, IFS_SWITCH = 40mA –87 dBc
fOUT = 5897MHz –73 dBc
fOUT = 8897MHz –74 dBc
fOUT = 8897MHz, IFS_SWITCH = 40mA –74 dBc
IMGDES FDACCLK - FOUT DES Image fOUT = 97MHz -66 dBc
fOUT = 2897MHz -62 dBc
fOUT = 2897MHz, IFS_SWITCH = 40mA -62 dBc
fOUT = 5897MHz -59 dBc
fOUT = 8897MHz -51 dBc
fOUT = 8897MHz, IFS_SWITCH = 40mA -51 dBc
IMD3 Third-order two tone intermodulation distortion fOUT = 97 +/- 10MHz, -7dBFS/tone –80 dBc
fOUT = 2897 +/- 10MHz, -7dBFS/tone -83 dBc
fOUT = 2897 +/- 10MHz, -7dBFS/tone, IFS_SWITCH = 40mA -63 dBc
fOUT = 5897 +/- 10MHz, -7dBFS/tone -72 dBc
fOUT = 8897 +/- 10MHz, -7dBFS/tone -65 dBc
fOUT = 8897 +/- 10MHz, -7dBFS/tone, IFS_SWITCH = 40mA -67 dBc
NSD Noise spectral density, large signal, sinusoidal output, DEM/Dither off fOUT = 97MHz, 70MHz offset from fOUT –170 dBc/Hz
fOUT = 2897MHz, 70MHz offset from fOUT –168 dBc/Hz
fOUT = 2897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –168 dBc/Hz
fOUT = 5897MHz, 70MHz offset from fOUT –166 dBc/Hz
fOUT = 8897MHz, 70MHz offset from fOUT –160 dBc/Hz
fOUT = 8897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –160 dBc/Hz
NSD Noise spectral density, large signal, sinusoidal output, DEM/Dither on fOUT = 97MHz, 70MHz offset from fOUT –160 dBc/Hz
fOUT = 2897MHz, 70MHz offset from fOUT –158 dBc/Hz
fOUT = 2897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –158 dBc/Hz
fOUT = 5897MHz, 70MHz offset from fOUT –156 dBc/Hz
fOUT = 8897MHz, 70MHz offset from fOUT –152 dBc/Hz
fOUT = 8897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –152 dBc/Hz
NSD Noise spectral density, small signal, sinusoidal output, DEM/Dither off AOUT = -20 dBFS, fOUT = 97MHz, 70MHz offset from fOUT –170 dBFS/Hz
AOUT = -20dBFS, fOUT = 2897MHz, 70MHz offset from fOUT –169 dBFS/Hz
AOUT = -20dBFS, fOUT = 2897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –169 dBFS/Hz
AOUT = -20dBFS, fOUT = 5897MHz, 70MHz offset from fOUT –168 dBFS/Hz
AOUT = -20dBFS, fOUT = 8897MHz, 70MHz offset from fOUT –167 dBFS/Hz
AOUT = -20dBFS, fOUT = 8897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –167 dBFS/Hz
NSD Noise spectral density, small signal, sinusoidal output, DEM/Dither on AOUT = -20dBFS, fOUT = 97MHz, 70MHz offset from fOUT –163 dBFS/Hz
AOUT = -20dBFS, fOUT = 2897MHz, 70MHz offset from fOUT –162 dBFS/Hz
AOUT = -20dBFS, fOUT = 2897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –162 dBFS/Hz
AOUT = -20dBFS, fOUT = 5897MHz, 70MHz offset from fOUT –160 dBFS/Hz
AOUT = -20dBFS, fOUT = 8897MHz, 70MHz offset from fOUT –160 dBFS/Hz
AOUT = -20dBFS, fOUT = 8897MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA –160 dBFS/Hz
NPR Noise power ratio, peak Signal spanning C-Band, 200MHz notch in center, IFS_SWITCH = 40mA 53 dBc
ENOB Effective number of bits Calculated from peak NPR 8.5 bits
PN Additive DAC phase noise, external clock contribution subtracted out, DEM/Dither off fOUT = 10GHz, 100Hz offset dBc/Hz
fOUT = 10GHz, 1kHz offset -120 dBc/Hz
fOUT = 10GHz, 10kHz offset -132 dBc/Hz
fOUT = 10GHz, 100kHz offset -140 dBc/Hz
fOUT = 10GHz, 1MHz offset -147 dBc/Hz
fOUT = 10GHz, 10MHz offset -149 dBc/Hz
22GSPS GSPS, JMODE 2, 4x Int, RF MODE
POUT Output power into 100Ω load(2) fOUT = 13103MHz -3.5 dBm
fOUT = 16103MHz -4.0 dBm
fOUT = 16103MHz, IFS_SWITCH = 40mA 2.0 dBm
fOUT = 19103MHz -5.0 dBm
SFDR Spurious free dynamic range (SFDR) across FDACCLK/2 - FDACCLK fOUT = 13103MHz –45 dBc
fOUT = 16103MHz -45 dBc
fOUT = 16103MHz, IFS_SWITCH = 40mA -45 dBc
fOUT = 19103MHz -45 dBc
HD2 2nd Harmonic Distortion in FDACCLK/2 - FDACCLK fOUT = 13103MHz –40 dBc
fOUT = 16103MHz -35 dBc
fOUT = 16103MHz, IFS_SWITCH = 40mA -35 dBc
fOUT = 19103MHz -46 dBc
HD3 3rd Harmonic Distortion in FDACCLK/2 - FDACCLK fOUT = 13103MHz –51 dBc
fOUT = 16103MHz -75 dBc
fOUT = 16103MHz, IFS_SWITCH = 40mA -55 dBc
fOUT = 19103MHz -56 dBc
SFDRNONHD23 non-HD2/3 SFDR across FDACCLK/2 - FDACCLK fOUT = 13103MHz -72 dBc
fOUT = 16103MHz -67 dBc
fOUT = 16103MHz, IFS_SWITCH = 40mA -65 dBc
fOUT = 19103MHz -69 dBc
IMD3 Third-order two tone intermodulation distortion fOUT = 13103 +/- 10MHz, -7dBFS/tone -55 dBc
fOUT = 16103 +/- 10MHz, -7dBFS/tone -55 dBc
fOUT = 16103 +/- 10MHz, -7dBFS/tone, IFS_SWITCH = 40mA -60 dBc
fOUT = 19103 +/- 10MHz, -7dBFS/tone -70 dBc
NSD Noise spectral density, large signal, sinusoidal output, DEM/Dither off fOUT = 13103MHz, 70MHz offset from fOUT -158 dBc/Hz
fOUT = 16103MHz, 70MHz offset from fOUT -155 dBc/Hz
fOUT = 16103MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA -155 dBc/Hz
fOUT = 19103MHz, 70MHz offset from fOUT -154 dBc/Hz
NSD Noise spectral density, large signal, sinusoidal output, DEM/Dither on fOUT = 13103MHz, 70MHz offset from fOUT -154 dBc/Hz
fOUT = 16103MHz, 70MHz offset from fOUT -152 dBc/Hz
fOUT = 16103MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA -152 dBc/Hz
fOUT = 19103MHz, 70MHz offset from fOUT -151 dBc/Hz
NSD Noise spectral density, small signal, sinusoidal output, DEM/Dither off fOUT = 13103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -165 dBFS/Hz
fOUT = 16103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -164 dBFS/Hz
fOUT = 16103MHz, AOUT = -20dBFS, 70MHz offset from fOUT, IFS_SWITCH = 40mA -164 dBFS/Hz
fOUT = 19103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -164 dBFS/Hz
NSD Noise spectral density, small signal, sinusoidal output, DEM/Dither on fOUT = 13103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -160 dBFS/Hz
fOUT = 16103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -159 dBFS/Hz
fOUT = 16103MHz, AOUT = -20dBFS, 70MHz offset from fOUT, IFS_SWITCH = 40mA -159 dBFS/Hz
fOUT = 19103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -158 dBFS/Hz
NPR Noise power ratio, peak Signal spanning Ku-Band, 300MHz notch in center, IFS_SWITCH = 40mA 48 dBc
ENOB Effective number of bits Calculated from peak NPR 7.8 bits
PN Additive DAC phase noise, external clock contribution subtracted out, DEM/Dither off fOUT = 17.8GHz, 100Hz offset -103 dBc/Hz
fOUT = 17.8GHz, 1kHz offset -115 dBc/Hz
fOUT = 17.8GHz, 10kHz offset -126 dBc/Hz
fOUT = 17.8GHz, 100kHz offset -135 dBc/Hz
fOUT = 17.8GHz, 1MHz offset -144 dBc/Hz
fOUT = 17.8GHz, 10MHz offset -148 dBc/Hz
22GSPS GSPS, JMODE 2, 4x Int, DES2xH MODE
POUT Output power into 100Ω load(2) fOUT = 13103MHz -1.2 dBm
fOUT = 16103MHz -2.0 dBm
fOUT = 16103MHz, IFS_SWITCH = 40mA 4.0 dBm
fOUT = 19103MHz -2.5 dBm
SFDR Spurious free dynamic range (SFDR) across FDACCLK/2- FDACCLK fOUT = 13103MHz –47 dBc
fOUT = 16103MHz -35 dBc
fOUT = 16103MHz, IFS_SWITCH = 40mA -30 dBc
fOUT = 19103MHz -58 dBc
HD2 2nd Harmonic Distortion in FDACCLK/2- FDACCLK fOUT = 13103MHz –47 dBc
fOUT = 16103MHz -35 dBc
fOUT = 16103MHz, IFS_SWITCH = 40mA -30 dBc
fOUT = 19103MHz -58 dBc
HD3 3rd Harmonic Distortion in FDACCLK/2- FDACCLK fOUT = 13103MHz –72 dBc
fOUT = 16103MHz -69 dBc
fOUT = 16103MHz, IFS_SWITCH = 40mA -70 dBc
fOUT = 19103MHz -67 dBc
SFDRNONHD23 non-HD2/3 SFDR across FDACCLK/2- FDACCLK fOUT = 13103MHz -72 dBc
fOUT = 16103MHz -73 dBc
fOUT = 16103MHz, IFS_SWITCH = 40mA -65 dBc
fOUT = 19103MHz -69 dBc
IMGDES FDACCLK - FOUT DES Image fOUT = 13103MHz -43 dBc
fOUT = 16103MHz -48 dBc
fOUT = 16103MHz, IFS_SWITCH = 40mA -48 dBc
fOUT = 19103MHz -39 dBc
IMD3 Third-order two tone intermodulation distortion fOUT = 13103 +/- 10MHz, -7dBFS/tone -66 dBc
fOUT = 16103 +/- 10MHz, -7dBFS/tone -68 dBc
fOUT = 16103 +/- 10MHz, -7dBFS/tone, IFS_SWITCH = 40mA -58 dBc
fOUT = 19103 +/- 10MHz, -7dBFS/tone -70 dBc
NSD Noise spectral density, large signal, sinusoidal output, DEM/Dither off fOUT = 13103MHz, 70MHz offset from fOUT -158 dBc/Hz
fOUT = 16103MHz, 70MHz offset from fOUT -155 dBc/Hz
fOUT = 16103MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA -155 dBc/Hz
fOUT = 19103MHz, 70MHz offset from fOUT -154 dBc/Hz
NSD Noise spectral density, large signal, sinusoidal output, DEM/Dither on fOUT = 13103MHz, 70MHz offset from fOUT -154 dBc/Hz
fOUT = 16103MHz, 70MHz offset from fOUT -152 dBc/Hz
fOUT = 16103MHz, 70MHz offset from fOUT, IFS_SWITCH = 40mA -152 dBc/Hz
fOUT = 19103MHz, 70MHz offset from fOUT -151 dBc/Hz
NSD Noise spectral density, small signal, sinusoidal output, DEM/Dither off fOUT = 13103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -165 dBFS/Hz
fOUT = 16103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -164 dBFS/Hz
fOUT = 16103MHz, AOUT = -20dBFS, 70MHz offset from fOUT, IFS_SWITCH = 40mA -164 dBFS/Hz
fOUT = 19103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -164 dBFS/Hz
NSD Noise spectral density, small signal, sinusoidal output, DEM/Dither on fOUT = 13103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -160 dBFS/Hz
fOUT = 16103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -159 dBFS/Hz
fOUT = 16103MHz, AOUT = -20dBFS, 70MHz offset from fOUT, IFS_SWITCH = 40mA -159 dBFS/Hz
fOUT = 19103MHz, AOUT = -20dBFS, 70MHz offset from fOUT -158 dBFS/Hz
NPR Noise power ratio, peak Signal spanning Ku-Band, 300MHz notch in center, IFS_SWITCH = 40mA 48 dBc
ENOB Effective number of bits Calculated from peak NPR 7.8 bits
PN Additive DAC phase noise, external clock contribution subtracted out, DEM/Dither off fOUT = 17.8GHz, 100Hz offset dBc/Hz
fOUT = 17.8GHz, 1kHz offset -115 dBc/Hz
fOUT = 17.8GHz, 10kHz offset -127 dBc/Hz
fOUT = 17.8GHz, 100kHz offset -135 dBc/Hz
fOUT = 17.8GHz, 1MHz offset -144 dBc/Hz
fOUT = 17.8GHz, 10MHz offset -148 dBc/Hz
(1) Measured single ended into 50Ω load
(2) A 100Ω load is equivalent to a 2:1 with 50Ω single ended load. Includes device die and package parasitics and output response. PCB and external component losses removed.