SBAU315B July   2018  – March 2025 ADS9224R , ADS9234R

 

  1.   1
  2.   ADS9224REVM-PDK
  3.   Trademarks
  4. 1Overview
    1. 1.1 ADS9224REVM-PDK Features
    2. 1.2 ADS9224REVM Features
  5. 2Analog Interface
    1. 2.1 Connectors for Signal Source
    2. 2.2 ADC Differential Input Signal Driver
      1. 2.2.1 Input Signal Path
    3. 2.3 ADS9224R Internal Reference
  6. 3Digital Interfaces
    1. 3.1 multiSPI for ADC Digital IO
  7. 4Power Supplies
  8. 5Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface (GUI) Software Installation
  9. 6Operation
    1. 6.1 EVM GUI Global Settings for ADC Control
    2. 6.2 Register Map Configuration Tool
    3. 6.3 Time Domain Display Tool
    4. 6.4 Spectral Analysis Tool
    5. 6.5 Histogram Tool
  10. 7ADS9224REVM Bill of Materials, PCB Layout, and Schematics
    1. 7.1 Bill of Materials
    2. 7.2 PCB Layout
    3. 7.3 Schematics
  11. 8Revision History

3.1 multiSPI for ADC Digital IO

The ADS9224REVM-PDK supports several interface modes, as detailed in the ADS9224R data sheet. In addition to the standard SPI modes (single-, dual-, and quad-SDO lines), the multiSPI modes support single- and dual-data output rates. The PHI is capable of operating at a 3.3-V logic level and is directly connected to the digital I/O lines of the ADC. Table 3-1 lists the test points available for probing the SPI pins in both SPI and parallel byte mode.

Table 3-1 SPI Test Points
Designator Signal Description
TP1 RST Asynchronous reset; active low.
TP2 READY/STR Indicates data-ready or strobe output for data capture.
TP3 SDO-0/0A SPI mode: data output 0 for channel A.
Parallel byte mode: least significant bit (LSB) from the data byte.
TP4 SDO-1/1A SPI mode: data output 1 for channel A.
Parallel byte mode: LSB+1 from the data byte.
TP6 SDO-2/2A SPI mode: data output 2 for channel A.
Parallel byte mode: LSB+2 from the data byte.
TP7 SDO-3/3A SPI mode: data output 3 for channel A.
Parallel byte mode: LSB+3 from the data byte.
TP9 SDO-4/0B SPI mode: data output 4 for channel A.
Parallel byte mode: LSB+4 from the data byte.
TP10 SDO-5/1B SPI mode: data output 5 for channel A.
Parallel byte mode: LSB+5 from the data byte.
TP11 SDO-6/2B SPI mode: data output 6 for channel A.
Parallel byte mode: LSB+6 from the data byte.
TP12 SDO-7/3B SPI mode: data output 7 for channel A.
Parallel byte mode: MSB from the data byte.
TP13 SCLK Clock input pin for the serial interface.
TP14 SDI Serial data input pin.
TP15 CS Chip-select input pin; active low.
TP16 CONVST Conversion start input pin.