SBAU338B October   2019  – September 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1EVM Overview
    1. 1.1 Caution and Warnings
    2. 1.2 Introduction
    3. 1.3 Kit Contents
    4. 1.4 Specifications
    5. 1.5 Device Information
  6. 2Hardware
    1. 2.1 Recommended Test Environment
    2. 2.2 Required Hardware
    3. 2.3 Hardware Setup
      1. 2.3.1 AFE79xx EVM and TSW14J58 EVM Connections
      2. 2.3.2 Power Supply Setup
  7. 3Software
    1. 3.1 Required Software
      1. 3.1.1 Software Installation Sequence
    2. 3.2 Latte Overview
      1. 3.2.1 Latte User Interface
      2. 3.2.2 Useful Latte Short-Cuts
  8. 4Implementation Results
    1. 4.1 AFE79xxEVM Configuration
      1. 4.1.1 Connect Latte to Board
      2. 4.1.2 Compile Libraries
      3. 4.1.3 Program AFE79xx EVM
      4. 4.1.4 TXDAC Evaluation
      5. 4.1.5 RXADC and FBADC Evaluation
    2. 4.2 AFE79xxEVM Configuration Modifications
      1. 4.2.1 Data Converter Clocks Settings
      2. 4.2.2 Data Rate and JESD Parameters
      3. 4.2.3 Steps to Modify NCO
      4. 4.2.4 Steps to Modify DSA
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Status Check and Troubleshooting Guidelines
      1. 6.1.1 AFE79xx EVM Status Indicators
      2. 6.1.2 TSW14J58EVM Status Indicators
    2.     Trademarks
  11. 7Revision History

4.1.3 Program AFE79xx EVM

Follow the below instructions to program the LMK04828 and AFE79xx on the AFE79xxEVM.

  1. Select the script named bringup.py and press F5. No errors are expected, ignore any warnings regarding SPI control, relinquish, or reset property. This step takes a few minutes.
  2. Check the Log window to monitor any errors. This step completes the AFE79xxEVM configuration. Current consumption into the AFE79xxEVM is approximately 3A.
  3. A mismatch FPGA bitfile version error indicates that the firmware does not match the configuration file. For bitfile version 204b, check that the physical position of jumper J35 is covering pins 2 and 3 (the two pins positioned furthest from the FPGA fan).
  4. An LOS error indicates that the SerDes RX is electrically idle and the TX output is not normal. Resolve this error by resending the data (the DAC pattern) and reconfiguring the AFE79xxEVM by rerunning bringup.py.
  5. GPIO warnings or sysref errors typically indicate supply voltage or current limitations. Verify the power supply to the AFE79xxEVM and verify that a 5.5V supply voltage and a 5A current limit is used. Restart the Latte UI and rerun the scripts.
AFE7900EVM AFE7920EVM TSW14J58EVM Latte Log After Successful bringup.pyFigure 4-3 Latte Log After Successful bringup.py