SBAU338B October   2019  – September 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1EVM Overview
    1. 1.1 Caution and Warnings
    2. 1.2 Introduction
    3. 1.3 Kit Contents
    4. 1.4 Specifications
    5. 1.5 Device Information
  6. 2Hardware
    1. 2.1 Recommended Test Environment
    2. 2.2 Required Hardware
    3. 2.3 Hardware Setup
      1. 2.3.1 AFE79xx EVM and TSW14J58 EVM Connections
      2. 2.3.2 Power Supply Setup
  7. 3Software
    1. 3.1 Required Software
      1. 3.1.1 Software Installation Sequence
    2. 3.2 Latte Overview
      1. 3.2.1 Latte User Interface
      2. 3.2.2 Useful Latte Short-Cuts
  8. 4Implementation Results
    1. 4.1 AFE79xxEVM Configuration
      1. 4.1.1 Connect Latte to Board
      2. 4.1.2 Compile Libraries
      3. 4.1.3 Program AFE79xx EVM
      4. 4.1.4 TXDAC Evaluation
      5. 4.1.5 RXADC and FBADC Evaluation
    2. 4.2 AFE79xxEVM Configuration Modifications
      1. 4.2.1 Data Converter Clocks Settings
      2. 4.2.2 Data Rate and JESD Parameters
      3. 4.2.3 Steps to Modify NCO
      4. 4.2.4 Steps to Modify DSA
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Status Check and Troubleshooting Guidelines
      1. 6.1.1 AFE79xx EVM Status Indicators
      2. 6.1.2 TSW14J58EVM Status Indicators
    2.     Trademarks
  11. 7Revision History

1.2 Introduction

The AFE79xxEVM includes a clocking and power method and runs off a single 5.5V supply. As shown in Figure 1-1, the RF inputs and outputs using miniature version A (SMA) connectors are on the top side of EVM. A reference clock (for example, 10MHz) to lock the onboard voltage-controlled crystal oscillator (VCXO) with the LMK04828, PLL-1 can be provided to the connector named LMK CLKIN (SMA J19).(1)

Figure 1-1 shows the bottom view of the AFE79xxEVM.

AFE7900EVM AFE7920EVM TSW14J58EVM AFE79xxEVM Bottom View Figure 1-1 AFE79xxEVM Bottom View

Use SMA J12 (REF_CLK_HIGH) or SMA J13 (REF_CLK_LOW) to feed an external reference clock to lock the PLLs in the AFE79xx. The USB connector and the 5.5V connector are on the right side of the board.

Use the TSW14J58 capture card along with the AFE79xx EVM. TSW14J58 supports a SerDes speed of up to 29.5Gbps. Refer to Figure 1-2 for the typical connection between the TSW14J58 EVM and the AFE79xx EVM.

AFE7900EVM AFE7920EVM TSW14J58EVM AFE79xxEVM and TSW14J58EVM Rev. A10 Figure 1-2 AFE79xxEVM and TSW14J58EVM Rev. A10
1. Many typical lab equipments have 10MHz oscillator output to synchronize multiple lab systems. The onboard LMK04828 can accept the 10MHz from external lab equipment to verify synchronization and coherency of the data capture and generation to the AFE79xx EVM.