SBAU394B April   2022  – August 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 Quick Start Guide
  6. 2Hardware
    1. 2.1 ADC Analog Input Signal Path
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 Power Supplies
    4. 2.4 ADC Input Clock (CLK) Options
    5. 2.5 Digital-to-Analog Converter (DAC)
    6. 2.6 Digital Interface
    7. 2.7 Connection to the PHI
    8. 2.8 Digital Header
  7. 3Software Installation
  8. 4EVM Configuration and GUI Operation
    1. 4.1 EVM Configuration
    2. 4.2 GUI Operation
      1. 4.2.1 EVM GUI Global Settings for ADC Control
      2. 4.2.2 Register Map Configuration Tool
      3. 4.2.3 Time Domain Display Tool
      4. 4.2.4 Spectral Analysis Tool
      5. 4.2.5 Histogram Tool
      6. 4.2.6 DAC Configuration Tool
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layout
    3. 5.3 Bill of Materials
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7References
  12. 8Revision History

2.2 ADC Connections and Decoupling

Figure 2-2 shows all connections to the ADS1285 (U10). Each power supply connection has 0.1-μF and 1-μF decoupling capacitors. Make sure these capacitors are physically close to the device and have a good connection to the respective ground plane (GND or AVSS). The supply connections pass through a set of jumpers (J15). These jumpers enable power supply current measurements by the removing the shunt and inserting an ammeter between the supply power and the ADC pin. Alternatively, remove the shunts on jumper J15 and apply an external power source directly to the corresponding supply pin if desired. For more information about the required voltage and current levels for an external supply, see the Section 2.3, Table 1-2, and the ADC data sheet.

ADS1285EVM-PDK ADS1285 Connections and Decoupling Figure 2-2 ADS1285 Connections and Decoupling

By default, the EVM IOVDD is configured for 3.3V operation. Install resistor R68 to connect IOVDD to CAPD and enable 1.8V operation. Do not use the PHI board when R68 is installed. The IOVDD absolute maximum voltage is 2.2V and the maximum operating voltage is 1.95V with R68 installed. Applying 3.3V with R68 installed causes permanent damage to the ADS1285.

Several digital pins have a 49.9Ω series resistor. These resistors smooth the edges of the digital signals to provide minimal overshoot and ringing. The CS, PWDN, and RESET pins each have a 100kΩ pull-up resistor. These resistors verify that the ADC powers up in a known state.