SBAU394B April   2022  – August 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 Quick Start Guide
  6. 2Hardware
    1. 2.1 ADC Analog Input Signal Path
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 Power Supplies
    4. 2.4 ADC Input Clock (CLK) Options
    5. 2.5 Digital-to-Analog Converter (DAC)
    6. 2.6 Digital Interface
    7. 2.7 Connection to the PHI
    8. 2.8 Digital Header
  7. 3Software Installation
  8. 4EVM Configuration and GUI Operation
    1. 4.1 EVM Configuration
    2. 4.2 GUI Operation
      1. 4.2.1 EVM GUI Global Settings for ADC Control
      2. 4.2.2 Register Map Configuration Tool
      3. 4.2.3 Time Domain Display Tool
      4. 4.2.4 Spectral Analysis Tool
      5. 4.2.5 Histogram Tool
      6. 4.2.6 DAC Configuration Tool
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layout
    3. 5.3 Bill of Materials
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7References
  12. 8Revision History

2.7 Connection to the PHI

The ADS1285EVM-PDK board communicates with the PHI through a shrouded, 60-pin connector, J6. There are two round standoffs next to J6 with Phillips-head screws. Connect the PHI to the EVM by first removing the screws, then attaching the PHI to the EVM, and then installing the screws into the standoffs. The screws secure the EVM to the PHI and makes sure the connection between the boards.

Table 2-3 lists the different PHI connection and their functions.

Table 2-3 PHI Connector Pin Functions
PHI Connector Pin Name PHI Connector Pin Function
5.5V J6[1] Power-supply source for the analog section of the EVM
GND J6[3] Ground
~RESET J6[6] ADC reset pin, active low
~PWDN J6[8] ADC power-down pin, active low
SYNC J6[10] ADC synchronization, active high
DIN_PHI J6[12] SPI: DIN from the ADC, PICO, or serial interface data in (pre-RTM GUI revision compatibility)
GPIO1 J6[14] General-purpose I/O 1 pin from the ADC
GPIO0 J6[16] General-purpose I/O 0 pin from the ADC
DIN_PHI J6[18] SPI: DIN from the ADC, PICO, or serial interface data in (RTM GUI revision compatibility)
~CS_ADC J6[22] SPI: CS, chip-select, or serial interface select, active low for the ADC
SCLK_PHI J6[24] SPI: Serial interface clock, or SCLK
CAPCLK_OUT J6[26] Output path for the PHI signal to synchronize captures with any delay from the EVM
CAPCLK_IN J6[28] Input path for the PHI signal to synchronize captures with any delay from the EVM
~DRDY J6[30] SPI: Data-ready signal for the ADS1285; active-low DRDY
ADC_CLK (input) J6[32] Input for the PHI to sense CLK
ADC_CLK (output) J6[34] Possible output for the PHI to provide CLK (not supported on the ADS1285EVM-PDK)
DOUT J6[38] SPI: Serial data output for the ADS1285, or POCI
~RST/PWDN_DAC J6[46] Reset or power-down input pin for the DAC1282
SYNC_DAC J6[48] Synchronize input pin for the DAC1282
WP J6[49] Write protection for the EEPROM
DVDD J6[50] Power-supply source for the digital section of the EVM
SW/TD_DAC J6[52] Switch control input or bitstream input pin for the DAC1282
~CS_DAC J6[54] SPI: Serial port chip select, or CS, for the DAC1282
SDA J6[56] I2C serial data for the EEPROM used to identify the EVM
SCL J6[58] I2C serial clock for the EEPROM used to identify the EVM
ID_PWR J6[59] Power-supply source for the EEPROM used to identify the EVM
GND J6[60] Ground