SBAU394B April   2022  – August 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 Quick Start Guide
  6. 2Hardware
    1. 2.1 ADC Analog Input Signal Path
    2. 2.2 ADC Connections and Decoupling
    3. 2.3 Power Supplies
    4. 2.4 ADC Input Clock (CLK) Options
    5. 2.5 Digital-to-Analog Converter (DAC)
    6. 2.6 Digital Interface
    7. 2.7 Connection to the PHI
    8. 2.8 Digital Header
  7. 3Software Installation
  8. 4EVM Configuration and GUI Operation
    1. 4.1 EVM Configuration
    2. 4.2 GUI Operation
      1. 4.2.1 EVM GUI Global Settings for ADC Control
      2. 4.2.2 Register Map Configuration Tool
      3. 4.2.3 Time Domain Display Tool
      4. 4.2.4 Spectral Analysis Tool
      5. 4.2.5 Histogram Tool
      6. 4.2.6 DAC Configuration Tool
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layout
    3. 5.3 Bill of Materials
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7References
  12. 8Revision History

2.8 Digital Header

In addition to the PHI, the EVM has a header connected to the digital lines that can be used to connect a logic analyzer or oscilloscope. This placement allows for easy access to the digital communications. Header J9 is connected to the digital lines between the ADS1285 and the PHI connector. Table 2-4 describes the digital header pins.

Table 2-4 Digital Header Pins
Signal Name Digital Header Pin
~RESET J9[1]
~PWDN J9[3]
SYNC J9[5]

GPIO1

 J9[7]
GPIO0 J9[9]

DIN_PHI

 J9[11]
~CS_ADC J9[13]
SCLK_PHI J9[15]
~DRDY J9[17]
ADC_CLK J9[19]
DOUT J9[21]
~RST/PWDN_DAC J9[23]
SYNC_DAC J9[25]
SW/TD_DAC J9[27]
~CS_DAC J9[29]