SBAU417A July   2025  – September 2025 AFE7952

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Recommended Test Environment
    2. 2.2 Required Hardware
    3. 2.3 Hardware Setup
      1. 2.3.1 AFE7952 EVM and TSW14J58 EVM Connections
      2. 2.3.2 Power Supply Setup
  7. 3Software
    1. 3.1 Required Software
      1. 3.1.1 Software Installation Sequence
    2. 3.2 Latte Overview
      1. 3.2.1 Latte User Interface
      2. 3.2.2 Useful Latte Short-Cuts
  8. 4Implementation Results
    1. 4.1 AFE7952EVM Configuration
      1. 4.1.1 Connect Latte to Board
      2. 4.1.2 Compile Libraries
      3. 4.1.3 Program AFE7952 EVM
      4. 4.1.4 TXDAC Evaluation
      5. 4.1.5 RXADC and FBADC Evaluation
    2. 4.2 AFE7952EVM Configuration Modifications
      1. 4.2.1 Data Converter Clocks Settings
      2. 4.2.2 Data Rate and JESD Parameters
      3. 4.2.3 Steps to Modify NCO
  9. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  10. 6Additional Information
    1. 6.1 Status Check and Troubleshooting Guidelines
      1. 6.1.1 AFE7952 EVM Status Indicators
      2. 6.1.2 TSW14J58 EVM
    2. 6.2 Trademarks
  11. 7Revision History

Device Information

The AFE7952 is a high performance, wide bandwidth multi-channel transceiver, that integrates four RF sampling transmitter chains, four RF sampling receiver chains, and two RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains allows the device to generate and receive 3G, 4G, and 5G signals from wireless base stations, while the wide bandwidth capability of the is designed for multi-band 4G and 5G base stations.

Each receiver chain includes a 25dB range digital step attenuator (DSA), followed by a 3GSPS analog-to-digital converter (ADC). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. The single or dual digital down converters (DDC) provide up to 600MHz of combined signal BW in dual DDC mode or 1200MHz BW in single DDC mode. In TDD mode, the receiver channel can be configured to dynamically switch between the traffic receiver (TDD RX) and wideband feedback receiver (TDD FB), with the capability of reusing the same analog input for both purposes.

Each transmitter chain includes a single or dual digital up-converters (DUCs) supporting up to 2400MHz for 2TX or 1200MHz BW for 4TX combined signal bandwidth. The output of the DUCs drives a 12GSPS DAC (digital-to-analog converter) with a mixed mode output option to enhance second or third Nyquist operations. The DAC output includes a variable gain amplifier (TX DSA) with a 40dB range and 1dB analog and 0.125dB digital steps.

The feedback path includes an 25dB range DSA driving a 3GSPS RF sampling ADC, followed by a DDC with up to 1200MHz bandwidth.