The ADS1278EVM is designed for easy connection to
an external controller. This design enables the user to test application code and
firmware on the ADS1278 without having to develop a custom PCB. This section
describes the specific connections required to use the ADS1278EVM with an external
controller. Figure 2-10 shows the
location of various headers and terminal blocks described in this section.
First, complete the following steps to prepare the ADS1278EVM board for use with an external controller:
- Remove the PHI board if still connected to the
EVM.
- Provide +6V and ground (GND) to terminal block
J10 from an external bench supply. Make sure the external controller also
connects to GND on the EVM.
- See Section 2.7 to connect an external clock to the ADS1278EVM. Alternatively, use the 27MHz oscillator included with the EVM by:
- Moving jumper JP1 to pins 2-3 (OSC_Y1) to enable the oscillator
- Moving jumper JP2 to pins 2-3 (EVMCLK) to select the oscillator
- Install jumpers on header J4 to configure the
ADC. For example, install jumpers on MODE0, MODE1, FORMAT0, FORMAT1, and
FORMAT2, while leaving CLKDIV open (high). These selections configure the ADC
for high-speed mode, SPI interface, and dynamic TDM DOUT mode. See the ADS1278 data sheet for more information regarding the different
modes of ADC operation.
Finally, make the
following connections to enable digital communication between the ADS1278EVM and the
external controller:
- Connect POCI (peripheral out, controller in) from
the controller to the DOUT1 pin on header J6 on the EVM.
- Connect SCLK from the controller to the SCLK pin
on header J6 on the EVM.
- Connect the DIN pin on header J6 on the EVM to
GND, do not leave floating.
- Connect an I/O pin from the controller to the
SYNC pin on header J6 on the EVM. This connection is
needed for robust power-up reset. Alternatively, tie the
SYNC pin to IOVDD for test purposes.
- Connect an I/O pin from the controller to the
DRDY pin on header J6 on the EVM.
DRDY is an output from the ADC, indicating when new
data are ready to be clocked out of the ADC. As shown in Figure 2-11, the
user-defined data collection routine monitors this pin (polling or interrupt)
and only transfers data after a falling edge.