SBOA444 November   2020 TMCS1100

 

  1.   Trademarks
  2. 1Introduction
  3. 2Implementation Block Diagram
  4. 3Hardware Implemenation
    1. 3.1 Analog Inputs
      1. 3.1.1 Voltage Measurement Analog Front End
      2. 3.1.2 Current Measurement Analog Front End
    2. 3.2 MSP432 LaunchPad Connections
    3. 3.3 PCB Layout Recommendations
  5. 4How to Implement Software for Metrology Testing
    1. 4.1 Setup
      1. 4.1.1 Clock
      2. 4.1.2 UART Setup for GUI Communication
      3. 4.1.3 Real-Time Clock (RTC)
      4. 4.1.4 Direct Memory Access (DMA)
      5. 4.1.5 ADC Setup
    2. 4.2 Foreground Process
      1. 4.2.1 Formulas
        1. 4.2.1.1 Standard Metrology Parameters
        2. 4.2.1.2 Power Quality Formulas
    3. 4.3 Background Process
      1. 4.3.1 per_sample_dsp( )
        1. 4.3.1.1 Voltage and Current ADC Samples
        2. 4.3.1.2 Pure Waveform Samples
        3. 4.3.1.3 Frequency Measurement and Cycle Tracking
      2. 4.3.2 LED Pulse Generation
      3. 4.3.3 Phase Compensation
  6. 5Metrology Accuracy Testing
    1. 5.1 Test Setup
    2. 5.2 Results
  7. 6Schematics
  8. 7References

Standard Metrology Parameters

This section briefly describes the formulas used for the voltage, current, power, and energy calculations. As previously described, voltage and current samples are obtained at a sampling rate of 7812.5 Hz. All of the samples that are taken in approximately 10 or 12 cycle frames are kept and used to obtain the RMS values for voltage and current for each phase.

The RMS, voltage overdeviation, and voltage underdeviation values are obtained with the following formulas:

Equation 7.
GUID-20201005-CA0I-QDGT-MFVK-GS0QCVVWDKNW-low.gif

Equation 8.
GUID-20201005-CA0I-8ZWX-DRHW-P0GZ6SN91WF7-low.gif

Equation 9.
GUID-20201005-CA0I-4QFG-JTXX-8PG0MMK4NJW5-low.gif

Equation 10.
GUID-20201005-CA0I-VCFW-F2DP-XJJGF13XCM1V-low.gif

where,

  • ph = V-I mapping being calculated [that is, V-IA (= 1) V-IB (= 2) and V-IC (= 3)]

  • Vph(n) = Voltage sample at a sample instant n

  • Voffset,ph = Offset used to subtract effects of the additive white Gaussian noise from the voltage converter. This is in units of mV.

  • VNom= Defined nominal voltage of design

  • Iph(n) = Each current sample at a sample instant n

  • Ioffset,ph = Offset used to subtract effects of the additive white Gaussian noise from the current converter. This is in units of µA.

  • Sample count = Number of samples within the present frame

  • Kv,ph = Scaling factor for voltage

  • Ki,ph = Scaling factor for current

Power and energy are calculated for active and reactive energy samples of one frame. These samples are phase-corrected and passed on to the foreground process, which uses the number of samples (sample count) to calculate phase active and reactive powers through the following formulas:

Equation 11.
GUID-20201005-CA0I-DWXT-WJSQ-L6JH5SJP8DGL-low.gif

Equation 12.
GUID-20201005-CA0I-32LN-GVVL-4DQQBGNDXNQ1-low.gif

Equation 13.
GUID-20201005-CA0I-3LN4-LLKB-44DWGPV8H2LQ-low.gif

Where,

  • V90(n) = Voltage sample at a sample instant ‘n’ shifted by 90°

  • KACT,ph = Scaling factor for active power

  • KREACT,ph = Scaling factor for reactive power

  • PACT_offset,ph = Offset used to subtract effects of crosstalk on the active power measurements from other currents

  • PREACT_offset,ph = Offset used to subtract effects of crosstalk on the reactive power measurements from other currents

Note that for reactive energy, the 90° phase shift approach is used for two reasons:

1. This approach allows accurate measurement of the reactive power for very small currents

2. This approach conforms to the measurement method specified by IEC and ANSI standards

The calculated mains frequency is used to calculate the 90 degrees-shifted voltage sample. Because the frequency of the mains varies, the mains frequency is first measured accurately to phase shift the voltage samples accordingly.

To get an exact 90° phase shift, interpolation is used between two samples. For these two samples, a voltage sample slightly more than 90 degrees before the most recent voltage sample and a voltage sample slightly less than 90 degrees before the most recent voltage sample are used. The phase shift implementation of the application consists of an integer part and a fractional part. The integer part is realized by providing an N samples delay. The fractional part is realized by a one-tap FIR filter. In the test software, a lookup table provides the filter coefficients that are used to create the fractional delays.

Using the calculated powers, energies are calculated with the following formulas :

Equation 14.
GUID-20201005-CA0I-CSH6-0GZ8-SD2FKGZZ3ZSS-low.gif

Equation 15.
GUID-20201005-CA0I-KJ7W-RNDS-XX4FLLJSFMKP-low.gif

Equation 16.
GUID-20201005-CA0I-XLHS-0XGQ-KPPLVBRBFLSQ-low.gif

The calculated energies are then accumulated into buffers that store the total amount of energy consumed since system reset. Note that these energies are different from the working variables used to accumulate energy for outputting energy pulses. There are three sets of buffers that are available: one for each V-I mapping. Within each set of buffers, the following energies are accumulated:

  1. Active import energy (active energy when active power ≥ 0)

  2. Active export energy (active energy when active power < 0)

  3. Fundamental active import energy (fundamental active energy when fundamental active power ≥ 0)

  4. Fundamental active export energy (fundamental active energy when fundamental active power < 0)

  5. React. Quad I energy (reactive energy when reactive power ≥ 0 and active power ≥ 0; inductive load)

  6. React. Quad II energy (reactive energy when reactive power ≥ 0 and active power < 0; capacitive generator)

  7. React. Quad III energy (reactive energy when reactive power < 0 and active power < 0; inductive generator)

  8. React. Quad IV energy (reactive energy when reactive power < 0 and active power ≥ 0; capacitive load)

  9. App. import energy (apparent energy when active power ≥ 0)

  10.  App. export energy (apparent energy when active power < 0)

The background process also calculates the frequency in terms of samples-per-mains cycle. The foreground process then converts this samples-per-mains cycle to Hertz with Equation 17:

Equation 17.
GUID-20201005-CA0I-RTNJ-CMNZ-ZWVT5SRLNBX2-low.gif

After the active power and apparent power have been calculated, the absolute value of the power factor is calculated. In the internal representation of power factor of the system, a positive power factor corresponds to a capacitive load; a negative power factor corresponds to an inductive load. The sign of the internal representation of power factor is determined by whether the current leads or lags voltage, which is determined in the background process. Therefore, the internal representation of power factor is calculated with the following equation:

Equation 18.
GUID-20201005-CA0I-GVTW-BFWK-XHWP2TV9J3L7-low.gif