Figure 7-1 shows a circuit example of the LOG200 driving a fully-differential input ADC. This circuit uses the auxiliary op amp in the inverting configuration to perform a single-ended to differential conversion for driving the ADS7954 fully-differential, SAR ADC.

Figure 7-1 LOG200 Driving a Fully-Differential Input ADC

Table 6-3 show the typical LOG200 specifications for error calculation:

Design Notes:

1. Select high-grade C0G (NP0) capacitors for C_DIFF, C_CM1, C_CM2 and C_FB to minimize distortion.
2. Use 0.1% resistors for R_IN and R_FB to minimize gain error and drift on the inverting amplifier circuit.
3. The R-C-R filter placed at the ADS7054 inputs drives the SAR as a charge kickback filter. The filter component values depend on the data converter sampling rate, the ADC sample-and-hold structure, and the data converter requirements. The filter combination (R_FIL and C_FIL) is tuned for ADC sample-and-hold settling performance while maintaining amplifier stability. The component value selection is dependent on the data converter sampling rate, the ADC sample-and-hold structure.
4. The values shown in this example provide good settling performance for the LOG200 and ADS7054 14-Bit, 1-MSPS, differential input, SAR ADC. If the circuit is modified, the circuit designer can need to select a different R-C-R filter depending on the ADC selection and application needs. See the Introduction to SAR ADC Front-End Component Selection training video for an explanation of how to select the RC filter for best settling performance.