SBOS115B June 1999 – January 2026 INA133 , INA2133
PRODUCTION DATA
5.5 Typical Characteristics
At TA = +25°C, VS = ±15 V, RL = 10 kΩ connected to ground, VREF = 0 V, and all chip site origins (CSO), unless otherwise noted.
Figure 5-1 Gain vs Frequency
Figure 5-3 Power Supply Rejection vs Frequency
Figure 5-5 Input Common-Mode Voltage vs Output Voltage
| CSO: RFB |
| CSO: RFB |
Figure 5-11 Quiescent Current vs Temperature
| CSO: SHE |
| CSO: RFB |
Figure 5-17 Offset Voltage Production Distribution VS = ±15V
Figure 5-19 Offset Voltage Drift Production Distribution VS = ±15V
Figure 5-21 Small-Signal Overshoot vs Load Capacitance
Figure 5-23 Small-Signal Step Response
| CSO: RFB |
Figure 5-2 Common-Mode Rejection vs Frequency
Figure 5-4 Channel Separation vs Frequency
| CSO: SHE |
| CSO: SHE |
Figure 5-10 0.1 Hz to 10 Hz Peak-to-Peak Voltage
Noise
| CSO: SHE |
| CSO: SHE |
| CSO: RFB |
Figure 5-18 Offset Voltage Production Distribution VS = ±5V
Figure 5-20 Offset Voltage Drift Production Distribution VS = ±5V
Figure 5-22 Settling Time vs Load Capacitance
| CSO: SHE |
Figure 5-26 Maximum Output Voltage vs Frequency