SBOS115B June   1999  – January 2026 INA133 , INA2133

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1.     7
    2. 5.1 Absolute Maximum Ratings
    3. 5.2 Recommended Operating Conditions
    4. 5.3 Thermal Information
    5. 5.4 Electrical Characteristics
    6. 5.5 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Gain Error and Drift
      2. 6.3.2 Input Voltage Range
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Operating Voltage
      2. 7.1.2 Input Voltage
      3. 7.1.3 Offset Voltage Trim
    2. 7.2 Typical Application
    3. 7.3 Additional Applications
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Development Support
        1. 8.1.2.1 PSpice® for TI
        2. 8.1.2.2 TINA-TI (Free Software Download)
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.4 Electrical Characteristics

at TA = 25°C, VS = ±15V, RL = 10kΩ connected to ground, VREF = 0V, G = 1, applies to all packages and part variants, and all chip site origins (CSO), unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Offset voltage RTO(1)(2), VCM = 0V U variant ±150 ±450 µV
UA variant ±150 ±900
RTO(1)(2), VCM = 0V, VS = ±5V U variant ±300 ±750
UA variant ±300 ±1500
Offset voltage drift RTO(1)(2), TA = –40°C to +85°C ±2 ±5 µV/℃

VS = ±5V
 		 ±2
PSRR Power-supply rejection ratio RTO(1)(2), VS = ±2.25V to ±18V U variant ±10 ±30 µV/V
UA variant 850 900 950
Long-term stability RTO(1)(2) 0.3 µV/√mo
ZIN-DM Differential impedance (3) 50 kΩ
ZIN-CM Common-mode impedance(3) VCM = 0V 25 kΩ
VCM Common-mode voltage range(4) VO = 0V, VS = ±15V and VS = ±5V Positive 2 x (V+) – 3 2 x (V+) – 2 V
Negative 2 x (V–) + 3 2 x (V–) + 2
CMRR Common-mode rejection ratio VS = ±15V and VS = ±5V, VCM = 2 x (V–) + 3 to 2 x (V+)–3, RS = 0Ω U variant 80 90 dB
UA variant 74 90
NOISE VOLTAGE
eN Voltage noise RTO(2)(5) f = 0.01Hz to 10Hz CSO: SHE 2 µVPP
f = 10Hz CSO: SHE 80 nV/√Hz
CSO: RFB 40
f = 100Hz CSO: SHE 60
CSO: RFB 21
f = 1kHz CSO: SHE 57
CSO: RFB 20
GAIN
G Initial gain VS = ±15V and VS = ±5V 1 V/V
GE Gain error VS = ±15V and VS = ±5V, (V-) + 1V ≤ VO ≤ (V+) - 1.5V U variant ±0.02 ±0.05 %
UA variant ±0.02 ±0.1
Gain drift TA = –40°C to +85°C ±1 ±10 ppm/°C
Gain nonlinearity VS = ±15V and VS = ±5V, (V-) + 1V ≤ VO ≤ (V+) - 1.5V U variant ±0.0001 ±0.001 % of FSR
UA variant ±0.0001 ±0.002
OUTPUT
VO Output voltage, gain error < 0.1% Positive, VS = ±15V and VS = ±5V (V+) - 1.5 (V+) - 1.3 V
RL = 100kΩ (V+) - 0.8
Negative, VS = ±15V and VS = ±5V (V-) + 1 (V-) - 0.8
RL = 100kΩ (V-) + 0.3
Capacitive load (stable operation) 1000 pF
ISC Short-circuit current Continuous to VS / 2 Sourcing CSO: SHE 32 mA
CSO: RFB 70
Sinking CSO: SHE 25
CSO: RFB 70
FREQUENCY RESPONSE
BW Bandwidth, –3dB 1.5 MHz
SR Slew rate CSO: SHE 5 V/µs
CSO: RFB 20
tS Settling time VSTEP = 10V, CL = 100pF 0.1% 4 µs
0.01% 5.5
Overload recovery time 50% Overdrive 4 µs
POWER SUPPLY
IQ Quiescent current (per amplifier) IO = 0A ±0.95 ±1.2 mA
VS = ±5V ±0.92 ±1.2
(1) Referred to output in unity-gain difference configuration.
(2) Includes effects of input bias and offset currents of the amplifier.
(3) 25kΩ resistors are ratio matched but have ±20% absolute value.
(4) Maximum input voltage without protection is 10V more than either ±15V supply (±25V). Limit IIN to 1mA.
(5) Includes effects of input current noise of the amplifier and thermal noise contribution of resistor network.