SBOS145B August   1993  – December 2025 INA105

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Gain Error and Drift
      2. 6.3.2 Input Voltage Range
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
    3. 7.3 Additional Applications
      1. 7.3.1 Operational Amplifier Circuits
      2. 7.3.2 Instrumentation Amplifier Circuits
      3. 7.3.3 Voltage Reference Circuits
      4. 7.3.4 Special Function Circuits
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
      2. 8.1.2 Development Support
        1. 8.1.2.1 PSpice® for TI
        2. 8.1.2.2 TINA-TI (Free Software Download)
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.4 Electrical Characteristics

at TA = 25°C, VS = ±15V, RL = 10kΩ, VREF = 0V, G = 1, and all chip site origins (CSO), unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Offset voltage RTO(1)(2) INA105AM, INA105BM 50 250 µV
INA105KP, KU 50 500
Offset voltage drift TA = –40°C to +85°C, RTO(1)(2) INA105AM 5 20 µV/℃
INA105BM 5 10
INA105KP, KU 5 20
PSRR Power-supply rejection ratio RTO(1)(2), VS = ±6V to ±18V INA105AM 1 25 µV/V
INA105BM 1 15
INA105KP, KU 1 25
Long-term stability RTO(1)(2) 20 µV/mo
ZIN-DM Differential impedance (3) 50 kΩ
ZIN-CM Common-mode impedance(3) 50 kΩ
VCM Operating common-mode input voltage(4) –20 20 V
VDM Operating differential-mode input voltage(4) –10 10 V
CMRR Common-mode rejection ratio(5) TA = –40°C to +125°C INA105AM 80 90 dB
INA105BM 86 100
INA105KP, KU 72 90
NOISE VOLTAGE
eN Voltage noise RTO(1)(6) fO = 10kHz CSO: SHE 60 nV/√Hz
CSO: RFB 50
fB = 0.01Hz to 10Hz 2.4 µVPP
GAIN
GE Gain error INA105AM, INA105BM ±0.005 ±0.01 %
INA105KP, KU ±0.01 ±0.025
Gain drift 1 5 ppm/°C
Gain nonlinearity ±0.0002 ±0.001 % of FSR
OUTPUT
Output voltage IO = –5mA, 20mA 10 12 V
Load capacitance stability 1000 pF
ISC Short circuit current
Continuous to VS / 2

 Sourcing CSO: SHE 40 mA
CSO: RFB 70
Sinking CSO: SHE 10
CSO: RFB 70
ZO Output Impedance 0.01 Ω
FREQUENCY RESPONSE
BW Bandwidth, –3dB 1 MHz
FPBW Full Power Bandwidth, –3dB VO = 20Vpp 30 50 kHz
SR Slew rate CSO: SHE 2 3 V/µs
CSO: RFB 22
tS Settling time 0.1%, VSTEP = 10V 4 µs
0.01%, VSTEP = 10V 5
0.01%, VCM-STEP = 10V, VDIFF = 0V 1.5
POWER SUPPLY
IQ Quiescent current VO = 0V ±1.5 ±2 mA
(1) Referred to output in unity-gain difference configuration. Note that this circuit has a gain of 2 for the operational amplifier's offset voltage and noise voltage.
(2) Includes effects of input bias and offset currents of the amplifier.
(3) 25kΩ resistors are ratio matched but have ±20% absolute value.
(4) Maximum input voltage without protection is 10V more than either ±15V supply (±25V). Limit IIN to 1mA.
(5) With zero source impedance.
(6) Includes effects of the input current noise of the amplifier and thermal noise contribution of resistor network.