SBOS622D July   2018  – May 2025 OPA855

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input and ESD Protection
      2. 8.3.2 Feedback Pin
      3. 8.3.3 Wide Gain-Bandwidth Product
      4. 8.3.4 Slew Rate and Output Stage
    4. 8.4 Device Functional Modes
      1. 8.4.1 Split-Supply and Single-Supply Operation
      2. 8.4.2 Power-Down Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TIA in an Optical Front-End System
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Optical Sensor Interface
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.4.2 Power-Down Mode

The OPA855 features a power-down mode to reduce the quiescent current to conserve power. Figure 6-23 and Figure 6-24 show the OPA855 transient response as the PD pin toggles between the disabled and enabled states.

The PD disable and enable threshold voltages are with reference to the negative supply. If the amplifier is configured with the positive supply at 3.3 V and the negative supply at ground, then the disable threshold voltage is 0.65 V and the enable threshold voltage is 1.8 V. If the amplifier is configured with ±1.65-V supplies, then the disable threshold voltage is –1 V and the enable threshold voltage is 0.15 V. If the amplifier is configured with ±2.5-V supplies, then the disable threshold voltage is –1.85 V and the enable threshold voltage is –0.7 V.

Figure 8-8 shows the switching behavior of a typical amplifier as the PD pin is swept down from the enabled to the disabled state. Similarly, Figure 8-9 shows the switching behavior of a typical amplifier as the PD pin is swept up from the disabled to the enabled state. The small difference in the switching thresholds between the down sweep and up sweep is due to the hysteresis designed into the amplifier to increase noise immunity on PD.

OPA855 Switching Threshold(PD Pin Swept From High to Low)Figure 8-8 Switching Threshold
(PD Pin Swept From High to Low)
OPA855 Switching Threshold ( PD Pin Swept From Low to High)Figure 8-9 Switching Threshold ( PD Pin Swept From Low to High)

Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When the amplifier is configured as a noninverting amplifier, the feedback (RF) and gain (RG) resistor network form a parallel load to the output of the amplifier. To protect the input stage of the amplifier, the OPA855 uses internal, back-to-back protection diodes between the inverting and noninverting input pins; see also Figure 8-3. In the power-down state, if the differential voltage between the input pins of the amplifier exceeds a diode voltage drop, an additional low-impedance path is created between the noninverting input pin and the output pin.