SBVA089A September 2020 – October 2023 TPS745-Q1
4 Pin Failure Mode Analysis (Pin FMA)
This section provides a Failure Mode Analysis (FMA) for the pins of the TPS745-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
- Pin short-circuited to Ground (see Table 4-2)
- Pin open-circuited (see Table 4-3)
- Pin short-circuited to an adjacent pin (see Table 4-4)
- Pin short-circuited to supply (see Table 4-5)
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Table 4-1 TI Classification of Failure Effects
| Class | Failure Effects |
|---|---|
| A | Potential device damage that affects functionality |
| B | No device damage, but loss of functionality |
| C | No device damage, but performance degradation |
| D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the TPS745-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the TPS745-Q1 data sheet.
Figure 4-1 Pin Diagram Adjustable
TPS745-Q1 DRV PackageFigure 4-2 Pin Diagram Fixed
TPS745-Q1 DRV Package
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | Output voltage will be near or at ground - Device will enter current limit. Device may cycle in and out of thermal shutdown depending on power dissipation. | B |
| FB/NC | 2 | [Adjustable Output] Device will stop regulating. VOUT becomes equal to VIN minus dropout because the pass fet is driven on as hard as possible. [Fixed Output] No effect. | B/D |
| GND | 3 | - | D |
| EN | 4 | Device will turn off. | B |
| PG | 5 | Power-good never asserts when the output voltage is at target, thus potentially effecting power sequencing. | B |
| IN | 6 | No output voltage. Input supply can be 0 V. | B |
Table 4-3 Pin FMA for Device Pins
Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | Output voltage is disconnected from load | B |
| FB/NC | 2 | [Adjustable Output] Error amplifier input is left
floating, output voltage will not equal to set voltage [Fixed Output] No effect |
B/D |
| GND | 3 | Device may disable | B |
| EN | 4 | Device may disable | B |
| PG | 5 | The power-good signal is not accessible. Power sequencing can be effected. | B |
| IN | 6 | No output voltage | B |
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Short with | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|---|
| OUT | 1 | FB/NC | 2 | \[Adjustable Ouput] VOUT will be set to VFB = 0.55 V [Fixed Output] No effect | B/D |
| FB/NC | 2 | GND | 3 | [Adjustable Ouput] Device will stop regulating. Vout becomes equal to VIN minus dropout becasue the pass fet is driven on as hard as possible [Fixed Output] No effect | B/D |
| GND | 3 | EN | 4 | Output is forced OFF, VOUT is 0.0 V | B |
| EN | 4 | PG | 5 | [Push-pull power good] Output voltage connected to the input voltage through the internal PG MOSFET body diode. Output voltage is increased. [Open drain power good] Power-good never asserts when the output voltage is at target, thus potentially effecting power sequencing | A/B |
| PG | 5 | IN | 6 | [Push-pull power good] Output voltage connected to the input voltage through the internal PG MOSFET body diode. Output voltage is increased. [Open drain power good] Power-good never asserts when the output voltage is at target, thus potentially effecting power sequencing | A/B |
Table 4-5 Pin FMA for Device Pins Short-Circuited to VIN Supply
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
OUT | 1 | Output is not Regulated. VOUT = VIN | B |
FB/NC | 2 | [Adjustable Output] FB pin will be damaged if Vin is higher than 2V [Fixed Output] No effect | A/D |
GND | 3 | No Output Voltage. Either input supply is at 0.0V, or input fuse is blown | B |
EN | 4 | Output is forced ON regardless of enable signal | B |
PG | 5 | [push-pull power good] Output voltage connected to the input voltage through the internal PG MOSFET body diode. Output voltage is increased. [open drain power good] Power-good functionality cannot operate correctly. PG can be damaged if the absolute maximum rating (6.5 V) is violated. | A/B |
IN | 6 | No Effect | D |
Figure 4-3 Pin Diagram Adjustable TPS745-Q1 DRB Package
Figure 4-4 Pin Diagram Fixed TPS745-Q1 DRB PackageTable 4-6 Pin FMA for Device Pins Short-Circuited to Ground
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | Output voltage will be near/at ground - Device will enter current limit. It may cycle in and out of thermal shutdown depending on power dissipation | B |
| NC | 2 | Improved Thermal Performance | D |
| FB/NC | 3 | [Adjustable Output] Device will stop regulating. VOUT becomes equal to VIN minus dropout because the pass fet is driven on as hard as possible. [Fixed Output] No effect. | B/D |
| GND | 4 | - | D |
| EN | 5 | Device will turn off. | B |
| PG | 6 | Power-good never asserts when the output voltage is at target, thus potentially effecting power sequencing. | B |
| NC | 7 | Improved Thermal Performance | D |
| IN | 8 | No output voltage. | B |
Table 4-7 Pin FMA for Device Pins Open-Circuited
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | Output voltage is disconnected from load. | B |
| NC | 2 | No Effect | D |
| FB/NC | 3 | [Adjustable Output] Error aplifier input is left floating, output voltage will not equal to set voltage. [Fixed Output] No effect. | B/D |
| GND | 4 | Device may disable. | B |
| EN | 5 | Device may disable. | B |
| PG | 6 | The power-good signal is not accessible. Power sequencing can be effected. | B |
| NC | 2 | No Effect | D |
| IN | 8 | No output voltage | B |
Table 4-8 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
| Pin Name | Pin No. | Short with | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|---|---|
| OUT | 1 | NC | 2 | Reduced thermal performance | D |
| NC | 2 | FB/NC | 3 | No Effect | D |
| FB/NC | 3 | GND | 4 | [Adjustable Ouput] Device will stop regulating. Vout becomes equal to VIN minus dropout becasue the pass fet is always on [Fixed Output] No effect | B/D |
| GND | 4 | EN | 5 | Output is forced OFF, VOUT is 0.0V | B |
| EN | 5 | PG | 6 | [Push-pull power good] Output voltage connected to the input voltage through the internal PG MOSFET body diode. Output voltage is increased. [Open drain power good] Power-good never asserts when the output voltage is at target, thus potentially effecting power sequencing | A/B |
| PG | 6 | NC | 7 | No Effect | D |
| NC | 7 | IN | 8 | Reduced thermal performance | D |
Table 4-9 Pin FMA for Device Pins Short-Circuited to VIN Supply
| Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
|---|---|---|---|
| OUT | 1 | Output is not Regulated. VOUT = VIN | B |
| NC | 2 | No Effect | D |
| FB/NC | 3 | [Adjustable Output] FB pin will be damaged if Vin is higher than 2 V [Fixed Output] No effect | A/D |
| GND | 4 | No Output Voltage. Either input supply is at 0.0 V, or input fuse is blown | B |
| EN | 5 | Output is forced ON regardless of enable signal | B |
| PG | 6 | [push-pull power good] Output voltage connected to the input voltage through the internal PG MOSFET body diode. Output voltage is increased. [open drain power good] Power-good functionality cannot operate correctly. PG can be damaged if the absolute maximum rating (6.5 V) is violated. | A/B |
| NC | 7 | No Effect | D |
| IN | 8 | No Effect | D |