SBVA089A September   2020  – October 2023 TPS745-Q1

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
  7. 5Revision History

Overview

This document contains information for TPS745-Q1 (DRV and DRBpackages) to aid in a functional safety system design. Information provided are:

  • Functional Safety Failure In Time (FIT) rates of the semiconductor component estimated by the application of industry reliability standards
  • Component failure modes and their distribution (FMD) based on the primary function of the device
  • Pin failure mode analysis (Pin FMA)

Figure 1-1 shows the Adjustable Version With Open-Drain Power-Good functional block diagram for reference.

Figure 1-2 shows the Adjustable Version With Push-Pull Power-Good functional block diagram for reference.

Figure 1-3 shows the Fixed Voltage Version With Open-Drain Power-Good functional block diagram for reference.

Figure 1-4 shows the Fixed Voltage Version With Push-Pull Power-Good functional block diagram for reference.

GUID-4AB33050-B06D-4459-A01D-1C13E485AF58-low.gifFigure 1-1 Adjustable Version With Open-Drain Power-Good
GUID-4C7A1A70-3D2C-4115-BB8E-A0A74EA02306-low.gif Figure 1-2 Adjustable Version With Push-Pull Power-Good
GUID-7A499015-3902-478E-8EA7-21BD3C0143A1-low.gif Figure 1-3 Fixed Voltage Version With Open-Drain Power-Good
GUID-5A9386EC-7500-4F2B-AAC2-C32B498CD8F1-low.gif Figure 1-4 Fixed Voltage Version With Push-Pull Power-Good

TPS745-Q1 was developed using a quality-managed development process, but was not developed in accordance with the IEC 61508 or ISO 26262 standards.