SCASE77A April   2025  – September 2025 TPUL2G123

PRODUCTION DATA  

  1.   1
  2.   2
  3. 1 Features
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     14
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 State Machine Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Naming Convention
      2. 7.3.2 Retriggerable One-Shot
      3. 7.3.3 Timing Mechanism and Accuracy
      4. 7.3.4 Balanced CMOS Push-Pull Outputs
      5. 7.3.5 CMOS Schmitt-Trigger Inputs
      6. 7.3.6 Latching Logic with Known Power-Up State
      7. 7.3.7 Partial Power Down (Ioff)
      8. 7.3.8 Clamp Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off-State Operation
      2. 7.4.2 Startup Operation
      3. 7.4.3 On-State Operation
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application - Edge Detector
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Timing Components
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
        4. 8.2.1.4 Power Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application - Delayed Pulse Generator
      1. 8.3.1 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Option Addendum
    2. 11.2 Tape and Reel Information
    3. 11.3 Mechanical Data

5.7 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter Measurement Information.
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC MIN TYP MAX UNIT
CL = 15pF
tpd T, T, or CLR Q or Q CL = 15pF 1.5V 13 28.6 64 ns
1.65V 10 23.1 51 ns
2.3V 6 13.7 28 ns
3V 5 9.8 20 ns
4.5V 3 7.1 14 ns
5.5V 3 6.3 13 ns
tt Q or Q CL = 15pF 1.5V 4.3 8.3 ns
1.65V 3.9 7 ns
2.3V 3 5.6 ns
3V 2.5 5 ns
4.5V 2.4 4.9 ns
5.5V 2.7 5.8 ns
CL = 50pF
tpd T, T, or CLR Q or Q CL = 50pF 1.5V 13 31.8 72 ns
1.65V 10 24.8 57 ns
2.3V 6 14.3 32 ns
3V 5 10.8 23 ns
4.5V 3 7.9 16 ns
5.5V 3 7 14 ns
two(1) Q or Q Rext = 10kΩ; Cext = 0; CL = 50pF 1.5V 129 405 ns
1.65V 116 311 ns
2.3V 87 161 ns
3V 75 118 ns
4.5V 62 96 ns
5.5V 58 88 ns
Rext = 10kΩ; Cext = 0.1µF; CL = 50pF 1.5V 814 996 µs
1.65V 815 997 µs
2.3V 815 997 µs
3V 815 997 µs
4.5V 805 985 µs
5.5V 793 971 µs
Δtwo(2) Q or Q CL = 50pF 1.5V to 5.5V ±1 ±10 %
tt Q or Q CL = 50pF 1.5V 8.2 34.4 ns
1.65V 7 28 ns
2.3V 4.5 24.6 ns
3V 3.9 17.4 ns
4.5V 3.1 12.6 ns
5.5V 2.9 8.7 ns
Cpd(3) CLR T = VCC, T = GND, fI = 10MHz, CL = 50pF, Cext = 0pF, Rext = 1MΩ 1.5V 42 pF
1.65V 41 pF
2.3V 40 pF
3V 32 pF
4.5V 35 pF
5.5V 38 pF
(1) Output pulse width
(2) Variation in output pulse width as compared to typical characteristics for K factor excluding variations in external timing components. Only applies within recommended operating conditions.
(3) Power dissipation capacitance is calculated in accordance with CMOS Power Consumption and Cpd Calculation.