SCASE79A April   2025  – September 2025 TPUL2T323

PRODUCTION DATA  

  1.   1
  2.   2
  3. 1 Features
  4. 2 Applications
  5. 3 Description
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7.     14
    8. 5.7 Switching Characteristics
    9. 5.8 Typical Characteristics
  8. 6 Parameter Measurement Information
  9. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Naming Convention
      2. 7.3.2 Retriggerable One-Shot
      3. 7.3.3 Extended RC Timed One-Shot
      4. 7.3.4 Balanced CMOS Push-Pull Outputs
      5. 7.3.5 CMOS Schmitt-Trigger Inputs
      6. 7.3.6 Latching Logic with Known Power-Up State
      7. 7.3.7 Partial Power Down (Ioff)
      8. 7.3.8 Reduced Input Threshold Voltages
      9. 7.3.9 Clamp Diode Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off-State Operation
      2. 7.4.2 Startup Operation
      3. 7.4.3 On-State Operation
  10. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application - Edge Detector
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Timing Components
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
        4. 8.2.1.4 Power Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application - Delayed Pulse Generator
      1. 8.3.1 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  11. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  12. 10Revision History
  13. 11Mechanical, Packaging, and Orderable Information

5.7 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter Measurement Information.
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS VCC MIN TYP MAX UNIT
CL = 15pF
tpd T, T, or CLR Q or Q CL = 15pF 1.5V 7 35 59 ns
1.65V 6 28.6 47
2.3V 4 16.6 26
3V 3 12.4 19
4.5V 2 9.4 13
5.5V 2 9.2 12
tt Q or Q CL = 15pF 1.5V 4.3 8.3 ns
1.65V 3.9 7
2.3V 3 5.6
3V 2.5 5
4.5V 2.4 4.9
5.5V 2.7 5.8
CL = 50pF
tpd T, T, or CLR Q or Q CL = 50pF 1.5V 7 37 67 ns
1.65V 6 30.2 53
2.3V 4 17.6 30
3V 3 13 22
4.5V 2 9.8 16
5.5V 2 9.6 14
two(1) Q or Q Rext = 1MΩ; Cext = 0; CL = 50pF 1.5V 2.3 3.6 4.4 ms
1.65V 2.5 3.5 4.3
2.3V 2.2 3.4 4.1
3V 2.2 3.3 4
4.5V 2.1 3.2 3.8
5.5V 2 3.1 3.8
Rext = 10kΩ; Cext = 0.1µF; CL = 50pF 1.5V 831 934 1017 ms
1.65V 832 934 1018
2.3V 837 932 1024
3V 842 938 1030
4.5V 852 949 1043
5.5V 857 954 1049
Rext = 330kΩ; Cext = 1µF; CL = 50pF 1.5V 261 295 324 s
1.65V 250 301 316
2.3V 253 298 315
3V 255 300 317
4.5V 261 306 320
5.5V 264 310 323
Δtwo(2) Q or Q CL = 50pF 1.5V to 5.5V ±1 ±10 %
tt Q or Q CL = 50pF 1.5V 8.2 34.4 ns
1.65V 7 28
2.3V 4.5 24.6
3V 3.9 17.4
4.5V 3.1 12.6
5.5V 2.9 8.7
Cpd(3) CLR T = VCC, T = GND fI = 10MHz CL = 50pF Cext = 0pF Rext = 1MΩ 1.5V 46 pF
1.65V 46
2.3V 49
3V 40
4.5V 47
5.5V 49
(1) Output pulse width
(2) Variation in output pulse width as compared to typical characteristics for K factor excluding variations in external timing components.
(3) Power dissipation capacitance is calculated in accordance with CMOS Power Consumption and Cpd Calculation.