SCEA065B November   2018  – March 2021 SN74AVC4T774 , SN74AXC1T45 , SN74AXC4T245 , SN74AXC4T774 , SN74AXC8T245 , SN74AXC8T245-Q1 , SN74AXCH1T45 , SN74AXCH4T245 , SN74AXCH8T245


  1.   Trademarks
  2. 1Introduction
  3. 2Common Interfaces and AXC Implementation
    1. 2.1 General Purpose Input Output (GPIO)
    2. 2.2 Serial Peripheral Interface (SPI)
      1. 2.2.1 Voltage Translation for SPI
      2. 2.2.2 SPI Applications
    3.     8
    4. 2.3 UART
      1. 2.3.1 Voltage Translation With UART
      2. 2.3.2 UART Applications
    5. 2.4 Joint Test Action Group (JTAG)
      1. 2.4.1 JTAG Applications
    6. 2.5 Reduced Gigabit Media Independent Interface (RGMII)
      1. 2.5.1 Voltage Translation for RGMII
      2. 2.5.2 RGMII Applications
      3. 2.5.3 Skew Performance
  4. 3Summary
  5. 4Related Documentation
  6. 5Revision History

Joint Test Action Group (JTAG)

Joint Test Action Group (JTAG) developed a hardware interface of the same name to allow debugging, testing, verification, and programming of embedded designs. JTAG usually operates using five lines: TCK, TMS, TDI, TDO, and TRST as listed in Table 2-2. Test Clock (TCK) provides the timing for the data input and output. Test Mode Select (TMS) allows the user to choose what will be tested. Test Data In (TDI) is where data to be tested is input to the device under test, the resulting output is carried on Test Data Out (TDO). The final signal, Test Reset (TRST), is optional and gives the ability to reset JTAG to the last known good state.

Table 2-2 JTAG Interface
TCKTest Clock SignalController to Debugger
TDITest Data InController to Debugger
TDOTest Data OutDebugger to Controller
TMSTest Mode SelectController to Debugger
TRSTTest ResetController to Debugger

Since JTAG is similar to SPI, the configuration of voltage translators is similar. The key difference is that JTAG has four lines running in one direction and one in the opposite direction. To enable use of JTAG interface between a low voltage FPGA or processor, and a JTAG probe, the SN74AXC4T774 or the SN74AVC4T774 device, as configured in Figure 2-10 is recommended. Alternatively, one SN74AXC4T245 for the TCK, TMS, TDI, and TRST signal lines, and one SN74AXC1T45 for the TDO line operating in the other direction can be used, for the five-line JTAG interface.

GUID-8D863BED-9DDE-4F79-B807-12B8C105F7BC-low.gifFigure 2-10 JTAG Voltage Translation Using SN74AXC4T774