1 Introduction

The DP83826x and DP83826Ax are a single-port physical layer transceivers compliant to IEEE802.3 10BASE-Te and 100BASE-TX standards. The DP83826x and DP83826Ax are designed to meet stringent industrial field bus application requirements and offers very low latency, deterministic variation in latency (across reset, power cycle), fixed phase between XI and TX_CLK, low power, and configuration using hardware bootstraps to achieve fast link up.

The devices support the standard MII and RMII (Leader mode and Follower mode) for direct connection to the media access controller (MAC). The device dedicated CLKOUT pin can be used to clock other modules on the system. In addition, the PWRDN pin controls the DP83826x and DP83826Ax link up from power-on-reset (POR) and helps with the design of asynchronous power-up of the DP83826x and DP83826Ax and host system-on-a-chip (SoC) or field-programmable-gate-array (FPGA) controller. The device operates from a single 3.3V power supply and has an integrated LDO to provide voltage rails required for internal blocks.

The device allows I/O voltage interfaces of 3.3V or 1.8V, which in turn enables the DP83826x and DP83826Ax to operate as a single-supply PHY when I/O voltage is 3.3V and a dual-supply PHY when I/O voltage is 1.8V. Automatic supply configuration within the DP83826x and DP83826Ax allows for any combination of VDDIO supply without the need for additional configuration settings. The DP83826x and DP83826Ax uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over a CAT5e twisted-pair cable.