SFFS661A November 2023 – September 2026 LMR38015-Q1 , LMR38025-Q1

4 Pin Failure Mode Analysis (Pin FMA)

This section provides a failure mode analysis (FMA) for the pins of the LMR38015-Q1 and LMR38025-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:

Pin short-circuited to ground (see Table 4-2)
Pin open-circuited (see Table 4-3)
Pin short-circuited to an adjacent pin (see Table 4-4)
Pin short-circuited to supply (see Table 4-5)

Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.

Table 4-1 TI Classification of Failure Effects

Class	Failure Effects
A	Potential device damage that affects functionality.
B	No device damage, but loss of functionality.
C	No device damage, but performance degradation.
D	No device damage, no impact to functionality or performance.

Figure 4-1 shows the LMR38015-Q1 and LMR38025-Q1 pin diagram. For a detailed description of the device pins please refer to the Pin Configuration and Functions section in the LMR38015-Q1 and LMR38025-Q1 datasheet.

Figure 4-1 Pin Diagram

Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:

Application circuit, as per the LMR38015-Q1 and LMR38025-Q1 datasheet

Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground

Pin Name	Pin No	Description of Potential Failure Effects	Failure Effect Class
GND	1	The device operated as normal.	D
GND	2	The device operated as normal.	D
EN	3	VOUT = 0V.	B
VIN	5	VOUT = 0V.	B
VIN	6	VOUT = 0V.	B
RT/SYNC	7	Switching frequency is greater than 3MHz.	C
FB	8	VOUT is greater than the programmed output voltage.	B
PG	9	There is no power good function.	B
BOOT	10	VOUT = 0V.	B
SW	11	There is damage to the high-side (HS) FET.	A
SW	12	There is damage to the high-side (HS) FET.	A

Table 4-3 Pin FMA for Device Pins Open-Circuited

Pin Name	Pin No	Description of Potential Failure Effects	Failure Effect Class
GND	1	VOUT is potentially abnormal due to switching noise on the analog circuits.	B
GND	2		B
EN	3	The device can shut off.	B
VIN	5	The device can shut off.	B
VIN	6	The device can shut off.	B
RT/SYNC	7	There is no Switching frequency.	B
FB	8	VOUT is greater than the programmed output voltage.	B
PG	9	There is no power good function.	B
BST	10	VOUT = 0V.	B
SW	11	VOUT = 0V.	B
SW	12	VOUT = 0V.	B

Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin

Pin Name 1	Pin Name 2	Description of Potential Failure Effects	Failure Effect Class
GND	EN	VOUT = 0V.	B
EN	VIN	VOUT operates as normal.	B
FB	PG	VOUT is less than the programmed output voltage.	B
PG	BOOT	The PG pin has ESD damage if the voltage of the BOOT pin is greater than 20V.	A
BOOT	SW	VOUT = 0V.	B

Table 4-5 Pin FMA for Device Pins Short-Circuited to Supply

Pin Name	Pin No	Description of Potential Failure Effects	Failure Effect Class
GND	1	VOUT = 0V. Damage to other pins is referred to GND.	A
GND	2	VOUT = 0V. Damage to other pins is referred to GND.	A
EN	3	The device is enabled.	D
VIN	5	The pin is in normal mode.	D
VIN	6	The pin is in normal mode.	D
RT/SYNC	7	There is ESD damage to the RT/SYNC pin if VIN > 5.5V.	A
FB	8	If VIN exceeds 5.5V, damage to the device occurs. VOUT = 0V.	A
PG	9	There is ESD damage to the PG pin if VIN > 20V.	B
BOOT	10	VOUT = 0V. The CBOOT ESD clamp runs the current to destruction.	A
SW	11	There is damage to the low-side (LS) FET.	A
SW	12	There is damage to the low-side (LS) FET.	A