SFFSAW7 November   2025 INA750B

 

  1.   1
  2.   Trademarks
  3. 1Overview
  4. 2Functional Safety Failure In Time (FIT) Rates
    1. 2.1 REM (VQFN – 14) Package
  5. 3Failure Mode Distribution (FMD)
  6. 4Pin Failure Mode Analysis (Pin FMA)
    1. 4.1 REM (VQFN – 14) Package
  7. 5Revision History

4.1 REM (VQFN – 14) Package

Figure 4-1 shows the INA75X-Q1 pin diagrams for the REM (VQFN – 14) package. For a detailed description of the device pins please refer to the corresponding Pin Configuration and Functions sections in the INA750x and INA751x datasheets.

INA75X-Q1 Pin Diagram REM (VQFN – 14) Package Figure 4-1 Pin Diagram REM (VQFN – 14) Package
Table 4-2 Pin FMA for Device Pins Short-Circuited to Ground
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
IN+ 1 A short from the bus supply to GND occurs. High current flows from the bus supply to GND. Damage to the internal bond wires is possible. A
NC 2 The device operates as normal. D
VS 3 The power supply is shorted to GND. There is no power to the device. B
NC 4 The device operates as normal. D
GND 5 The device operates as normal. D
NC 6 The device operates as normal. D
IS– 7 In a high-side configuration, a short from the bus supply to GND occurs. High current flows from the bus supply to GND. The shunt is potentially damaged due to high current. A
In a low-side configuration, normal operation. D
IN– 8 In a high-side configuration, a short from the bus supply to GND occurs. High current flows from the bus supply to GND. Damage to the internal bond wires is possible. A
In a low-side configuration, normal operation. D
NC 9 The device operates as normal. D
OUT 10 The output is shorted to GND. B
FB 11 The output voltage becomes unpredictable. B
REF 12 The device operates as normal if REF = GND by design. D
If REF ≠ GND by design, the functionality of the device is affected. B
ALERT 13 The ALERT pin is forced to active mode. There is a loss of the functionality of the ALERT pin. B
IS+ 14 A short from the bus supply to GND occurs in a high-side configuration. The functionality of the system is affected in a high-side or low-side configuration. B
Table 4-3 Pin FMA for Device Pins Open-Circuited
Pin NamePin No.Description of Potential Failure EffectsFailure Effect Class
IN+1The device operates as normal.D
NC2The device operates as normal.D
VS3There is no power to the device.B
NC4The device operates as normal.D
GND5There is no power to the device.B
NC6The device operates as normal.D
IS–7The bus supply to the load path is cut off and load current does not flow.C
IN–8The device operates as normal.D
NC9The device operates as normal.D
OUT10The output can be left open.C
FB11The output becomes unpredictableB
REF12The output becomes unpredictableB
ALERT13The ALERT pin is open. There is a loss of the functionality of the ALERT pin.B
IS+14The bus supply to the load path is cut off and load current does not flow.C
Table 4-4 Pin FMA for Device Pins Short-Circuited to Adjacent Pin
Pin Name Pin No. Shorted to Description of Potential Failure Effects Failure Effect Class
IN+ 1 2 – NC The device operates as normal. D
NC 2 3 – VS The device operates as normal. D
VS 3 4 – NC The device operates as normal. D
NC 4 5 – GND The device operates as normal. D
GND 5 6 – NC The device operates as normal. D
NC 6 7 – IS– In a high-side configuration, damage to the device is possible. A
In a low-side configuration, the device operates as normal. D
IS– 7 8 – IN– The device operates as normal. D
IN– 8 9 – NC The device operates as normal. D
NC 9 10 – OUT The device operates as normal. D
OUT 10 11 – FB The device operates as normal if the OUT pin is shorted to the FB pin by design D
If the OUT pin is not shorted to the FB pin by design, the functionality of the device is affected. C
FB 11 12 – REF The functionality of the output is affected. C
REF 12 13 – ALERT The functionalities of both the output and ALERT pins are affected. B
ALERT 13 14 – IS+ In a high-side configuration, damage to the device is possible. A
In a low-side configuration, there is a loss of the functionality of the ALERT pin. B
IS+ 14 1 – IN+ The device operates as normal. D
Table 4-5 Pin FMA for Device Pins Short-Circuited to VS
Pin Name Pin No. Description of Potential Failure Effects Failure Effect Class
IN+ 1 In a low-side configuration, a short from the pin VS to GND occurs. In a high-side configuration, the bus supply is shorted to the VS pin. Damage to the device is possible. A
NC 2 The device operates as normal. D
VS 3 The device operates as normal. D
NC 4 The device operates as normal. D
GND 5 The power supply is shorted to GND. There is no power to the device. B
NC 6 There is a slight increase in quiescent current. The device functionality not affected. C
IS– 7 In a high-side configuration, a short from the bus supply to the VS pin occurs. High current flows from the bus supply to the VS pin or from the VS pin to the bus supply. Damage to the device is possible. A
In a low-side configuration, the functionality of the system is affected negatively but the device is not negatively affected. C
IN– 8 In a high-side configuration, a short from the bus supply to the VS pin occurs. High current flows from the bus supply to the VS pin or from the VS pin to the bus supply. Damage to the device is possible. A
In a low-side configuration, the functionality of the system is affected negatively but the device is not negatively affected. C
NC 9 The device operates as normal. D
OUT 10 The output is shorted to the power supply. B
FB 11 The output becomes unpredictable. B
REF 12 The device operates as normal if REF = VS by design. D
If REF ≠ VS by design, the functionality of the device is affected. B
ALERT 13 There is a loss of the functionality of the ALERT pin. B
IS+ 14 In a low-side configuration, a short from the VS pin to GND occurs. In a high-side configuration, the bus supply is shorted to the VS pin. Damage to the device is possible. A