SGLS274H September   2008  – October 2016 UCC27423-Q1 , UCC27424-Q1 , UCC27425-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
      3. 8.3.3 Enable
      4. 8.3.4 Parallel Outputs
      5. 8.3.5 Operational Waveforms and Circuit Layout
      6. 8.3.6 VDD
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Source and Sink Capabilities During Miller Plateau
        2. 9.2.2.2 Drive Current and Power Requirements
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8 Detailed Description

8.1 Overview

The UCC2742x-Q1 family of high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads. The UCC27423-Q1 offers these standard logic options: dual-inverting drivers, dual noninverting drivers, and one inverting, one noninverting driver. The thermally enhanced 8-pin PowerPAD MSOP package (DGN) drastically lowers the thermal resistance to improve long-term reliability. It is also offered in the standard 8-pin SOIC (D) package. Using a design that inherently minimizes shoot-through current, these drivers deliver 4 A of current where it is needed most at the Miller plateau region during the MOSFET switching transition. A unique Bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages.

8.2 Functional Block Diagram

UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 fbd_gls274.gif

8.3 Feature Description

8.3.1 Input Stage

The input thresholds have a 3.3-V logic sensitivity over the full range of VDD voltages; yet it is equally compatible with 0 to VDD signals. The inputs of UCC2742x-Q1 drivers are designed to withstand 500-mA reverse current without either damage to the IC for logic upset. The input stage of each driver must be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (< 200 ns). The input stages to the drivers function as a digital gate, and they are not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency.

Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power device, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the device package, as discussed in the Thermal Considerations section.

8.3.2 Output Stage

Inverting outputs of the UCC2742x-Q1 are intended to drive external P-channel MOSFETs. Noninverting outputs of the UCC2742x-Q1 are intended to drive external N-channel MOSFETs.

Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The pullup and pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the external MOSFET. This means that in many cases, external Schottky-clamp diodes are not required.

The UCC2742x-Q1 family delivers the 4-A gate drive where it is most needed during the MOSFET switching transition—at the Miller plateau region—providing improved efficiency gains. A unique bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.

8.3.3 Enable

UCC2742x-Q1 provide dual enable inputs for improved control of each driver channel operation. The inputs incorporate logic-compatible thresholds with hysteresis. They are internally pulled up to VDD with 100-kΩ resistor for active-high operation. When ENBA and ENBB are driven high, the drivers are enabled; when ENBA and ENBB are low, the drivers are disabled. The default state of the enable pin is to enable the driver and, therefore, can be left open for standard operation. The output states when the drivers are disabled is low, regardless of the input state. See Table 1 for operation using enable logic.

Enable inputs are compatible with both logic signals and slowly-changing analog signals. They can be directly driven, or a power-up delay can be programmed with a capacitor between ENBA/ENBB and GND. ENBA and ENBB control input A and input B, respectively.

8.3.4 Parallel Outputs

The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in Figure 28.

UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 paral_out_cx_gls274.gif Figure 28. Parallel Outputs

8.3.5 Operational Waveforms and Circuit Layout

Figure 29 shows the circuit performance achievable with a single driver (half of the 8-pin IC) driving a 10-nF load. The input pulse width (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linear rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.

UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 puls_respons_gls274.gif Figure 29. Pulse Response

In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much overshoot or undershoot and ringing. The low output impedance of these drivers produces waveforms with high di/dt. This tends to induce ringing in the parasitic inductances. Use the upmost care in the circuit layout. It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground on the opposite side of the output, so the ground must be connected to the bypass capacitors and the load with copper trace as wide as possible. These connections must also be made with a small enclosed loop area to minimize the inductance.

8.3.6 VDD

Although quiescent VDD current is very low, total supply current is higher, depending on OUTA and OUTB current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from Equation 1.

Equation 1. IOUT = Qg × f

where

  • f is frequency

For the best high-speed circuit performance, TI recommends two VDD bypass capacitors to prevent noise problems. TI highly recommends using surface-mount components. A 0.1-µF ceramic capacitor must be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1 µF) with relatively low ESR must be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors must present a low impedance characteristic for the expected current levels in the driver application.

8.4 Device Functional Modes

With VDD power supply in the range of 4 V to 16 V, the output stage is dependent on the states of the HI and LI pins. Table 1 shows the UCC2742x-Q1 truth table.

Table 1. Input and Output Logic Table

ENBA ENBB INPUTS (VIN_L, VIN_H) UCC27423-Q1 UCC27424-Q1 UCC27425-Q1
INA INB OUTA OUTB OUTA OUTB OUTA OUTB
H H L L H H L L H L
H H L H H L L H H H
H H H L L H H L L L
H H H H L L H H L H
L L X X L L L L L L

Importantly, if INA and INB are not used, they must be tied to either VDD or GND; they must not be left floating.