SGLS274H September   2008  – October 2016 UCC27423-Q1 , UCC27424-Q1 , UCC27425-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
      3. 8.3.3 Enable
      4. 8.3.4 Parallel Outputs
      5. 8.3.5 Operational Waveforms and Circuit Layout
      6. 8.3.6 VDD
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Source and Sink Capabilities During Miller Plateau
        2. Drive Current and Power Requirements
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

11 Layout

11.1 Layout Guidelines

Optimum performance of gate drivers cannot be achieved without taking due considerations during circuit board layout. The following points are emphasized:

  1. Low ESR or ESL capacitors must be connected close to the IC between VDD and GND pins to support high peak currents drawn from VDD during the turnon of the external MOSFETs.
  2. Grounding considerations:
    • The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gates to a minimal physical area. This decreases the loop inductance and minimizes noise issues on the gate terminals of the MOSFETs. The gate driver must be placed as close as possible to the MOSFETs.
    • Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM controller at one, single point. The connected paths must be as short as possible to reduce inductance.
    • Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals during transition. The ground plane must not be a conduction path for any current loop. Instead the ground plane must be connected to the star-point with one single trace to establish the ground potential. In addition to noise shielding, the ground plane can help in power dissipation as well.
  3. In noisy environments, tying inputs of an unused channel of the UCC2742x-Q1 device to VDD or GND using short traces in order to ensure that the output is enabled and to prevent noise from causing malfunction in the output may be necessary.
  4. Separate power traces and signal traces, such as output and input signals.

11.2 Layout Example

UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 PCB_layout_UCC2742x.gif Figure 35. Recommended PCB Layout for UCC2742x-Q1

11.3 Thermal Considerations

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the IC package. For a power driver to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC2742x-Q1 family of drivers is available in three different packages to cover a range of application requirements.

As shown in the power dissipation rating table, the 8-pin SOIC (D) package has a power rating of around 0.5 W with TA = 70°C. This limit is imposed in conjunction with the power derating factor also given in the Dissipation Ratings table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD, switched at 300 kHz. Thus, only one load of this size could be driven using the D package, even if the two onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages.

The 8-pin MSOP with PowerPAD (DGN) package significantly relieves this concern by offering an effective means of removing the heat from the semiconductor junction. As described in reference 2 of the Related Documentation section, the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PCB directly underneath the IC package, reducing the RθJC(bot) down to 5.9°C/W. Data is presented in reference 2 of Related Documentation to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages. The PCB must be designed with thermal lands and thermal vias to complete the heat removal subsystem. This allows a significant improvement in heat sinking over that available in the D package, and is shown to more than double the power capability of the D package. Note that the PowerPAD is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which is the ground of the device.