SGLS274H September   2008  – October 2016 UCC27423-Q1 , UCC27424-Q1 , UCC27425-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
      3. 8.3.3 Enable
      4. 8.3.4 Parallel Outputs
      5. 8.3.5 Operational Waveforms and Circuit Layout
      6. 8.3.6 VDD
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Source and Sink Capabilities During Miller Plateau
        2. 9.2.2.2 Drive Current and Power Requirements
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

6 Pin Configuration and Functions

UCC27423-Q1: D or DGN Package
8-Pin SOIC or MSOP With PowerPAD
Top View
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 pinout_1.gif
Dual Inverting
UCC27424-Q1: D or DGN Package
8-Pin SOIC or MSOP With PowerPAD
Top View
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 pinout_2.gif
Dual Noninverting
UCC27425-Q1: D or Package
8-Pin SOIC
Top View
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 pinout_3.gif
One inverting, one noninverting

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 ENBA I Enable input for the driver A with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. The output state when the device is disabled is low, regardless of the input state.
2 INA I Input A. Input signal of the A driver which has logic-compatible threshold and hysteresis. If not used, this input must be tied to either VDD or GND. It must not be left floating.
3 GND Common ground. This ground must be connected very closely to the source of the power MOSFET which the driver is driving.
4 INB I Input B. Input signal of the A driver which has logic-compatible threshold and hysteresis. If not used, this input must be tied to either VDD or GND. It must not be left floating.
5 OUTB O Driver output B. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
6 VDD Supply voltage and the power input connection for this device.
7 OUTA O Driver output A. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET.
8 ENBB I Enable input for the driver B with logic-compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active-high operation. The output state when the device is disabled is low, regardless of the input state.