SGLS274H September   2008  – October 2016 UCC27423-Q1 , UCC27424-Q1 , UCC27425-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Dissipation Ratings
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stage
      2. 8.3.2 Output Stage
      3. 8.3.3 Enable
      4. 8.3.4 Parallel Outputs
      5. 8.3.5 Operational Waveforms and Circuit Layout
      6. 8.3.6 VDD
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Source and Sink Capabilities During Miller Plateau
        2. 9.2.2.2 Drive Current and Power Requirements
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VDD Supply voltage –0.3 16 V
IOUT Output current DC 0.3 A
Pulsed, 0.5 µs 4.5
VIN Input voltage INA, INB –5 6(3) or
(VDD + 0.3)(3)
V
VEN Enable voltage ENBA, ENBB –0.3 6(3) or
(VDD + 0.3)(3)
V
PD Power dissipation TA = 25°C (D package) 650 mW
TA = 25°C (DGN package) 3 W
TJ Junction operating temperature –55 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into, negative out of, the specified terminal.
(3) Whichever is larger.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 ±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Supply voltage 4 15 V
INA Input voltage –2 15 V
INB
ENA Enable voltage 0 15 V
ENB
TJ Operating junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) UCC2742x-Q1 UNIT
D
(SOIC)
DGN
(MSOP With PowerPAD)
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 112.6 63 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.5 53.8 °C/W
RθJB Junction-to-board thermal resistance 52.8 35.6 °C/W
ψJT Junction-to-top characterization parameter 15.8 1.9 °C/W
ψJB Junction-to-board characterization parameter 52.3 35.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 11.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

VDD = 4.5 V to 15 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT (INA, INB)
VIH Logic 1 input threshold 2 V
VIL Logic 0 input threshold 1 V
IIN Input current VIN = 0 V to VDD –10 0 10 μA
OUTPUT (OUTA, OUTB)
IOUT Output current VDD = 14 V(1) (2) 4 A
VOH High-level output voltage VOH = VDD – VOUT, IOUT = –10 mA, VDD = 14 V 330 450 mV
VOL Low-level output voltage IOUT = 10 mA, VDD = 14 V 22 40 mV
ROH Output resistance high TA = 25°C, IOUT = –10 mA, VDD = 14 V(3) 25 30 35 Ω
TA = full range, IOUT = –10 mA, VDD = 14 V(3) 18 45
ROL Output resistance low TA = 25°C, IOUT = 10 mA, VDD = 14 V(3) 1.9 2.2 2.5 Ω
TA = full range, IOUT = 10 mA, VDD = 14 V(3) 1.2 4
Latch-up protection(1) 500 mA
ENABLE (ENBA, ENBB)
VIN_H High-level input voltage Low-to-high transition 1.7 2.4 2.9 V
VIN_L Low-level input voltage High-to-low transition 1.1 1.8 2.2 V
Hysteresis 0.15 0.55 0.9 V
RENBL Enable impedance VDD = 14 V, ENBL = GND 75 100 145
OVERALL
IDD Operating current Static, VDD = 15 V, ENBA = ENBB = 15 V UCC27423-Q1 INA = 0 V INB = 0 V 900 1350 µA
INB = High 750 1100
INA = High INB = 0 V 750 1100
INB = High 600 900
UCC27424-Q1 INA = 0 V INB = 0 V 300 450
INB = High 750 1100
INA = High INB = 0 V 750 1100
INB = High 1200 1800
UCC27425-Q1 INA = 0 V INB = 0 V 600 900
INB = High 1050 1600
INA = High INB = 0 V 450 700
INB = High 900 1350
Disabled, VDD = 15 V, ENBA = ENBB = 0 V All INA = 0 V INB = 0 V 300 450
INB = High 450 700
INA = High INB = 0 V 450 700
INB = High 600 900
(1) Specified by design
(2) The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors.
(3) The pullup and pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.

7.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING TIME
tr Rise time (OUTA, OUTB) CLOAD = 1.8 nF(1) 20 40 ns
tf Fall time (OUTA, OUTB) CLOAD = 1.8 nF(1) 15 40 ns
tD1 Delay time, IN rising (IN to OUT) CLOAD = 1.8 nF(1) 25 50 ns
tD2 Delay time, IN falling (IN to OUT) CLOAD = 1.8 nF(1) UCC27423-Q1, UCC27424-Q1 35 60 ns
UCC27425-Q1 35 70
ENABLE (ENBA, ENBB)
tD3 Propagation delay time(3) CLOAD = 1.8 nF(1)(2) 30 60 ns
tD4 Propagation delay time(3) CLOAD = 1.8 nF(1)(2) 100 150 ns
(1) Specified by design
(2) Not production tested
(3) See Figure 2
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 sw_wav_driv_gls274.gif
The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation.
Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 sw_wav_enabl_gls274.gif
The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation.
Figure 2. Switching Waveform for Enable to Output

7.7 Dissipation Ratings

PACKAGE θJC (°C/W) θJA (°C/W) POWER RATING TA = 70°C (mW)(1)
D (SOIC-8) 42 84 to 160(2) 344 to 655(2)
DGN (MSOP PowerPAD)(3) 11.9 63 873
(1) 125°C operating junction temperature is used for power rating calculations.
(2) The range of values indicates the effect of the PCB. These values are intended to give the system designer an indication of the best- and worst-case conditions. In general, the system designer should attempt to use larger traces on the PCB, where possible, to spread the heat away form the device more effectively.
(3) The PowerPAD is not directly connected to any leads of the package. However, it is electronically and thermally connected to the substrate which is the ground of the device.

7.8 Typical Characteristics

UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_07_gls274.gif
VDD = 4.5 V
Figure 3. Supply Current vs Frequency
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_09_gls274.gif
VDD = 12 V
Figure 5. Supply Current vs Frequency
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_11_gls274.gif
CLOAD = 2.2 nF
Figure 7. Supply Current vs Supply Voltage
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_13_gls274.gif
Figure 9. Supply Current
vs Supply Voltage (UCC274323)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 tc_supcur8_lus545.gif
Figure 11. Supply Current
vs Supply Voltage (UCC27425-Q1)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_17_gls274.gif
Figure 13. Rise Time
vs Supply Voltage
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_19_gls274.gif
Figure 15. Delay Time (tD1)
vs Supply Voltage (UCC27423)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_21_gls274.gif
Figure 17. Enable Threshold and Hysteresis
vs Temperature
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_23_gls274.gif
Figure 19. Output Behavior
vs Supply Voltage (Inverting)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_25_gls274.gif
Figure 21. Output Behavior
vs VDD (Inverting)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_27_gls274.gif
Figure 23. Output Behavior
vs VDD (Noninverting)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_29_gls274.gif
Figure 25. Output Behavior
vs VDD (Noninverting)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_31_gls274.gif
Figure 27. Input Threshold
vs Temperature
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_08_gls274.gif
VDD = 8 V
Figure 4. Supply Current vs Frequency
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_10_gls274.gif
VDD = 15 V
Figure 6. Supply Current vs Frequency
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_12_gls274.gif
CLOAD = 4.7 nF
Figure 8. Supply Current vs Supply Voltage
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_14_gls274.gif
Figure 10. Supply Current
vs Supply Voltage (UCC27424)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_16_gls274.gif
Figure 12. Rise Time and Fall Time
Temperature (UCC27423)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_18_gls274.gif
Figure 14. Fall Time
vs Supply Voltage
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_20_gls274.gif
Figure 16. Delay Time (tD2)
vs Supply Voltage (UCC27423)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_22_gls274.gif
Figure 18. Enable Resistance
vs Temperature
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_24_gls274.gif
Figure 20. Output Behavior
vs Supply Voltage (Inverting)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_26_gls274.gif
Figure 22. Output Behavior
vs VDD (Inverting)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_28_gls274.gif
Figure 24. Output Behavior
vs VDD (Noninverting)
UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 typ_char_30_gls274.gif
Figure 26. Output Behavior
vs VDD (Noninverting)