SLAAE84B March   2023  – September 2025 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346

 

  1.   1
  2. Description
  3. Required Peripherals
  4. Design Steps
  5. Design Considerations
  6. Software Flow Chart
  7. Design Results
  8. Additional Resources
  9. E2E
  10. Trademarks
  11. 10Revision History

Design Considerations

  1. Maximum Sampling Speed: The sampling speed of the ADC is based on input signal frequency, analog front end, filters, or any other design parameters that affect sampling.
  2. ADC Reference: Choose the reference to align with the expected maximum input to utilize the full scale range of the ADC.
  3. Clock Settings: The clock source determines the total time for the conversion. The clock divider in tandem with the SCOMP setting determines the total sampling time. SysConfig sets the appropriate SCOMP depending on the sampling time setting.