SLAAET4 April   2025 MSPM0G3506 , MSPM0G3507 , MSPM0G3518 , MSPM0G3519

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 MCAN Features
  5. 2Sysconfig Configuration for MCAN Module
    1. 2.1 MCAN Clock Frequency
    2. 2.2 MCAN Basic Configuration
      1. 2.2.1 Transmitter Delay Compensation (TDC)
      2. 2.2.2 Bit Timing Parameters
      3. 2.2.3 Message RAM Configuration
        1. 2.2.3.1 Standard and Extended ID Filter Configuration
          1. 2.2.3.1.1 How to Add More Filters
        2. 2.2.3.2 TX MSG RAM
        3. 2.2.3.3 RX MSG RAM
    3. 2.3 Advanced Configuration
    4. 2.4 Retention Configuration
    5. 2.5 Interrupts
    6. 2.6 Pin Configuration and PinMux
  6. 3Demo Project Descriptions
    1. 3.1 TX Buffer Mode
    2. 3.2 TX FIFO Mode
    3. 3.3 RX Buffer Mode
    4. 3.4 RX FIFO Mode
  7. 4Debug and Design Tips to Resolve/Avoid CAN Communication Issues
    1. 4.1 Minimum Number of Nodes Required
    2. 4.2 Why a Transceiver is Needed
    3. 4.3 Bus Off Status
    4. 4.4 Using MCAN in Low Power Mode
    5. 4.5 Debug Checklist
      1. 4.5.1 Programming Issues
      2. 4.5.2 Physical Layer Issues
      3. 4.5.3 Hardware Debug Tips
  8. 5Summary
  9. 6References

2.2.1 Transmitter Delay Compensation (TDC)

Figure 2-1 shows what parameters are included in Transmitter Delay Compensation (TDC) block.

Transmitter Delay Compensation (TDC) Figure 2-3 Transmitter Delay Compensation (TDC)

TDC is a mechanism used to compensate for the delay caused by the loop delay of the transceiver in CAN FD systems. This delay can prevent nodes from performing meaningful bit error checks at the sample point during high-bit-rate data transmission. Specifically, TDC introduces a secondary sample point (Secondary Sample Point or SSP) in the data phase, where the transmitted bit is compared with the received bit after accounting for the delay. This makes sure that the bit errors are correctly detected and handled.

TDC is necessary when the bit rate is high, leading to short data bits and significant loop delays. These delays can cause the node to miss the correct sample point for bit error detection. TDC is only active during the data phase and does not affect the arbitration phase.

By using TDC, the data phase can have a shorter bit time than the nominal bit time, enabling higher data rates without compromising error detection.

  • TDC Filter Window Length (Cycles): this filter feature defines a minimum value for the SSP position to avoid the case in which a dominant glitch inside the received FDF bit ends the delay compensation measurement before the falling edge of the received res bit, resulting in an early taken SSP position.
  • TDC Offset (Cycles): this offset is used to adjust the position of the SSP inside the received bit (for example, half of the bit time in the data phase).

For more information about how to measure TDC, refer to the MSPM0 G-Series 80MHz Microcontrollers technical reference manual.