SLAAET4 April   2025 MSPM0G3506 , MSPM0G3507 , MSPM0G3518 , MSPM0G3519

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 MCAN Features
  5. 2Sysconfig Configuration for MCAN Module
    1. 2.1 MCAN Clock Frequency
    2. 2.2 MCAN Basic Configuration
      1. 2.2.1 Transmitter Delay Compensation (TDC)
      2. 2.2.2 Bit Timing Parameters
      3. 2.2.3 Message RAM Configuration
        1. 2.2.3.1 Standard and Extended ID Filter Configuration
          1. 2.2.3.1.1 How to Add More Filters
        2. 2.2.3.2 TX MSG RAM
        3. 2.2.3.3 RX MSG RAM
    3. 2.3 Advanced Configuration
    4. 2.4 Retention Configuration
    5. 2.5 Interrupts
    6. 2.6 Pin Configuration and PinMux
  6. 3Demo Project Descriptions
    1. 3.1 TX Buffer Mode
    2. 3.2 TX FIFO Mode
    3. 3.3 RX Buffer Mode
    4. 3.4 RX FIFO Mode
  7. 4Debug and Design Tips to Resolve/Avoid CAN Communication Issues
    1. 4.1 Minimum Number of Nodes Required
    2. 4.2 Why a Transceiver is Needed
    3. 4.3 Bus Off Status
    4. 4.4 Using MCAN in Low Power Mode
    5. 4.5 Debug Checklist
      1. 4.5.1 Programming Issues
      2. 4.5.2 Physical Layer Issues
      3. 4.5.3 Hardware Debug Tips
  8. 5Summary
  9. 6References

2.2.3.3 RX MSG RAM

Figure 2-6 shows what parameters are included in RX MSG RAM block.

RX MSG RAM Figure 2-7 RX MSG RAM

Up to 64 Rx buffers and two Rx FIFOs can be configured in the Message RAM. Each Rx FIFO section can be configured to store up to 64 received messages. The element size can be configured for storage of CAN FD messages with up to 64 bytes data field.

  • RX FIFO0 and RX FIFO1 Start Address: defines the start address of Rx FIFOs in message RAM.
  • Number of RX FIFO0 and RX FIFO1 Elements: each Rx FIFO can be configured to store up to 64 received messages.
  • RX FIFO0 and RX FIFO1 Watermark: the Rx FIFO watermark can be used to prevent an Rx FIFO overflow. If the Rx FIFO fill level reaches the Rx FIFO watermark, then an interrupt flag MCAN_IR.RF0W/MCAN_IR.RF1W is set.
  • RX FIFO0 and RX FIFO1 Operation Mode:
    • Rx FIFO Blocking Mode: the Rx FIFO blocking mode is the default operation mode for the Rx FIFOs. If an Rx FIFO full condition is reached, then no further messages are written to the corresponding Rx FIFO until at least one message is read out and the Rx FIFO Get Index is incremented.
    • Rx FIFO Overwrite Mode: when an Rx FIFO full condition is reached, the next accepted message for the FIFO overwrites the oldest FIFO message.
  • RX FIFO0 and RX FIFO1 Element Size: defines the Rx FIFO element size.
  • RX Buffer Start Address: defines the start address of Rx buffer in message RAM.
  • RX Buffer Element Size: defines the Rx buffer element size.