SLASF63A June   2023  – July 2025 DAC539E4W

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Threshold DAC
    6. 5.6  Electrical Characteristics: Comparator
    7. 5.7  Electrical Characteristics: General
    8. 5.8  Timing Requirements: I2C Standard Mode
    9. 5.9  Timing Requirements: I2C Fast Mode
    10. 5.10 Timing Requirements: I2C Fast Mode Plus
    11. 5.11 Timing Requirements: SPI Write Operation
    12. 5.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 5.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 6.3.2 Threshold DAC
        1. 6.3.2.1 Voltage Reference and DAC Transfer Function
          1. 6.3.2.1.1 Power-Supply as Reference
          2. 6.3.2.1.2 Internal Reference
          3. 6.3.2.1.3 External Reference
      3. 6.3.3 Look-Up Table (LUT)
      4. 6.3.4 Programming Interface
      5. 6.3.5 Nonvolatile Memory (NVM)
        1. 6.3.5.1 NVM Cyclic Redundancy Check (CRC)
          1. 6.3.5.1.1 NVM-CRC-FAIL-USER Bit
          2. 6.3.5.1.2 NVM-CRC-FAIL-INT Bit
      6. 6.3.6 Power-On Reset (POR)
      7. 6.3.7 External Reset
      8. 6.3.8 Register-Map Lock
    4. 6.4 Device Functional Modes
      1. 6.4.1 Comparator Mode
        1. 6.4.1.1 Programmable Hysteresis Comparator
      2. 6.4.2 Power-Down Mode
    5. 6.5 Programming
      1. 6.5.1 SPI Programming Mode
      2. 6.5.2 I2C Programming Mode
        1. 6.5.2.1 F/S Mode Protocol
        2. 6.5.2.2 I2C Update Sequence
          1. 6.5.2.2.1 Address Byte
          2. 6.5.2.2.2 Command Byte
        3. 6.5.2.3 I2C Read Sequence
    6. 6.6 Register Maps
      1. 6.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 6.6.2  DAC-x-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
      3. 6.6.3  DAC-x-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
      4. 6.6.4  DAC-x-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0401h]
      5. 6.6.5  DAC-x-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
      6. 6.6.6  COMMON-CONFIG Register (address = 1Fh) [reset = 1249h]
      7. 6.6.7  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      8. 6.6.8  COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      9. 6.6.9  GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      10. 6.6.10 CMP-STATUS Register (address = 23h) [reset = 0000h]
      11. 6.6.11 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      12. 6.6.12 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      13. 6.6.13 STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      14. 6.6.14 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      15. 6.6.15 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      16. 6.6.16 DAC-x-DATA Register (SRAM address = 21h, 22h, 23h, 24h) [reset = 8000h]
      17. 6.6.17 LUT-x-DATA Register (SRAM address = 25h through 34h) [reset = (see register description)]
      18. 6.6.18 LOOP-WAIT Register (SRAM address = 35h) [reset = 0000h]
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.6.16 DAC-x-DATA Register (SRAM address = 21h, 22h, 23h, 24h) [reset = 8000h]

Note: This register address is mapped to SRAM. Use the SRAM-CONFIG and SRAM-DATA registers to read and write.
Figure 6-32 DAC-x-DATA Register (x = 0, 1, 2, 3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DAC-x-DATA[9:0] X
R/W-800h X-0h
Table 6-31 DAC-x-DATA Register Field Descriptions
Bit Field Type Reset Description
15-4 DAC-x-DATA[9:0] R/W 800h Data for threshold DAC
Data are in straight-binary format. MSB left-aligned. Use the following bit-alignment:
{DAC-x-DATA[9:0], X, X}
X = Don't care bits.
3-0 X X 0h Don't care.