8.6.21 DMACHMAP3 Register (Offset = 0x51C) [reset = 0x0]
DMA Channel Map Select 3 (DMACHMAP3)
Each 4-bit field of the DMACHMAP3 register configures the µDMA channel assignment as specified in .
DMACHMAP3 is shown in Figure 8-30 and described in Table 8-40.
Return to Summary Table.
Figure 8-30 DMACHMAP3 Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| CH31SEL |
CH30SEL |
CH29SEL |
CH28SEL |
| R/W-0h |
R/W-0h |
R/W-0h |
R/W-0h |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| CH27SEL |
CH26SEL |
CH25SEL |
CH24SEL |
| R/W-0h |
R/W-0h |
R/W-0h |
R/W-0h |
|
Table 8-40 DMACHMAP3 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-28 |
CH31SEL |
R/W |
0x0 |
µDMA Channel 31 Source Select
See for channel assignments.
|
| 27-24 |
CH30SEL |
R/W |
0x0 |
µDMA Channel 30 Source Select
See for channel assignments.
|
| 23-20 |
CH29SEL |
R/W |
0x0 |
µDMA Channel 29 Source Select
See for channel assignments.
|
| 19-16 |
CH28SEL |
R/W |
0x0 |
µDMA Channel 28 Source Select
See for channel assignments.
|
| 15-12 |
CH27SEL |
R/W |
0x0 |
µDMA Channel 27 Source Select
See for channel assignments.
|
| 11-8 |
CH26SEL |
R/W |
0x0 |
µDMA Channel 26 Source Select
See for channel assignments.
|
| 7-4 |
CH25SEL |
R/W |
0x0 |
µDMA Channel 25 Source Select
See for channel assignments.
|
| 3-0 |
CH24SEL |
R/W |
0x0 |
µDMA Channel 24 Source Select
See for channel assignments.
|