| 31-12 |
RESERVED |
R |
0x0 |
|
| 11 |
RXFFIC |
W |
0x0 |
Receive FIFO Full Interrupt Clear. Writing a 1 to this bit clears the RXFFIS bit in the I2CMRIS register and the RXFFMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 10 |
TXFEIC |
W |
0x0 |
Transmit FIFO Empty Interrupt Clear Writing a 1 to this bit clears the TXFERIS bit in the I2CMRIS register and the TXFEMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 9 |
RXIC |
W |
0x0 |
Receive FIFO Request Interrupt Clear Writing a 1 to this bit clears the RXRIS bit in the I2CMRIS register and the RXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 8 |
TXIC |
W |
0x0 |
Transmit FIFO Request Interrupt Clear. Writing a 1 to this bit clears the TXRIS bit in the I2CMRIS register and the TXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 7 |
ARBLOSTIC |
W |
0x0 |
Arbitration Lost Interrupt Clear. Writing a 1 to this bit clears the ARBLOSTRIS bit in the I2CMRIS register and the ARBLOSTMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 6 |
STOPIC |
W |
0x0 |
STOP Detection Interrupt Clear. Writing a 1 to this bit clears the STOPRIS bit in the I2CMRIS register and the STOPMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 5 |
STARTIC |
W |
0x0 |
START Detection Interrupt Clear. Writing a 1 to this bit clears the STARTRIS bit in the I2CMRIS register and the STARTMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 4 |
NACKIC |
W |
0x0 |
Address/Data NACK Interrupt Clear. Writing a 1 to this bit clears the NACKRIS bit in the I2CMRIS register and the NACKMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 3 |
DMATXIC |
W |
0x0 |
Transmit DMA Interrupt Clear. Writing a 1 to this bit clears the DMATXRIS bit in the I2CMRIS register and the DMATXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 2 |
DMARXIC |
W |
0x0 |
Receive DMA Interrupt Clear. Writing a 1 to this bit clears the DMARXRIS bit in the I2CMRIS register and the DMARXMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 1 |
CLKIC |
W |
0x0 |
Clock Time-out Interrupt Clear. Writing a 1 to this bit clears the CLKRIS bit in the I2CMRIS register and the CLKMIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|
| 0 |
IC |
W |
0x0 |
Master Interrupt Clear. Writing a 1 to this bit clears the RIS bit in the I2CMRIS register and the MIS bit in the I2CMMIS register. A read of this register returns no meaningful data.
|