25.3.4 SHA_DMAIC Register (Offset = 0x1C) [reset = 0x0]
SHA DMA Interrupt Clear (SHA_DMAIC)
The SHA DMA Interrupt Clear register is used to clear the SHA_DMA_RIS and SHA_DMA_MIS registers by writing a 1 to each register bit.
NOTE
This registers always reads as zero.
SHA_DMAIC is shown in Figure 25-17 and described in Table 25-30.
Return to Summary Table.
Figure 25-17 SHA_DMAIC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
COUT |
DIN |
CIN |
| R-0x0 |
W1C-0x0 |
W1C-0x0 |
W1C-0x0 |
|
Table 25-30 SHA_DMAIC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-3 |
RESERVED |
R |
0x0 |
|
| 2 |
COUT |
W1C |
0x0 |
Context Out DMA Done Masked Interrupt Status.
Writing a 1 to this bit clears the COUT bit in the SHA_DMA_RIS and SHA_DMA_MIS register. |
| 1 |
DIN |
W1C |
0x0 |
Data In DMA Done Interrupt Clear.
Writing a 1 to this bit clears the DIN bit in the SHA_DMA_RIS and SHA_DMA_MIS register. |
| 0 |
CIN |
W1C |
0x0 |
Context In DMA Done Raw Interrupt Status.
Writing a 1 to this bit clears the CIN bit in the SHA_DMA_RIS and SHA_DMA_MIS register.. |