25.3.3 SHA_DMAMIS Register (Offset = 0x18) [reset = 0x0]
SHA DMA Masked Interrupt Status (SHA_DMAMIS)
The SHA DMA Masked Interrupt Status (SHA_DMA_MIS) register displays the raw interrupts that are unmasked in the SHA_DMA_RIS register.
SHA_DMAMIS is shown in Figure 25-16 and described in Table 25-29.
Return to Summary Table.
Figure 25-16 SHA_DMAMIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
COUT |
DIN |
CIN |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 25-29 SHA_DMAMIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-3 |
RESERVED |
R |
0x0 |
|
| 2 |
COUT |
R |
0x0 |
Context Out DMA Done Masked Interrupt Status
0x0 = An interrupt has not occurred or is masked.
0x1 = A COUT interrupt has occurred.
|
| 1 |
DIN |
R |
0x0 |
Data In DMA Done Masked Interrupt Status
0x0 = An interrupt has not occurred or is masked.
0x1 = A DIN interrupt has occurred.
|
| 0 |
CIN |
R |
0x0 |
Context In DMA Done Raw Interrupt Status
0x0 = An interrupt has not occurred or is masked.
0x1 = A CIN interrupt has occurred.
|