SLAU892A March   2023  – June 2024 AFE11612-SEP

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 Hardware Setup
      1. 2.1.1 Electrostatic Discharge Caution
      2. 2.1.2 Power Configurations and Jumper Settings
      3. 2.1.3 Connecting the Hardware
    2. 2.2 Hardware Description
      1. 2.2.1 Theory of Operation
        1. 2.2.1.1 Signal Definitions
  7. 3Software
    1. 3.1 Software Setup
      1. 3.1.1 Operating Systems
      2. 3.1.2 Software Installation
    2. 3.2 Software Description
      1. 3.2.1 Starting the Software
      2. 3.2.2 Software Features
        1. 3.2.2.1 High Level Configuration Page
          1. 3.2.2.1.1 DACs Subpage
          2. 3.2.2.1.2 ADCs Subpage
          3. 3.2.2.1.3 Alarms Subpage
          4. 3.2.2.1.4 GPIO + Temp Subpage
        2. 3.2.2.2 Low Level Configuration Page
  8. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Related Documentation from Texas Instruments
  11. 7Revision History

2.2.1.1 Signal Definitions

The AFE11612EVM provides access to all pins on the device through seven pin connectors.Table 3-3 and Table 3-4 list the pin definitions for connectors J7 and J21, respectively, which contain the DAC output pins connections for the AFE11612-SEP.

Table 2-3 AFE11612EVM J7 Pin Definitions
Pin# Signal Description
1 DAC6 Output pin for DAC6
2 GND Ground
3 DAC7 Output pin for DAC7
4 GND Ground
5 DAC8 Output pin for DAC8
6 GND Ground
7 DAC9 Output pin for DAC9
8 GND Ground
9 DAC10 Output pin for DAC10
10 GND Ground
11 DAC11 Output pin for DAC11
12 GND Ground
Table 2-4 AFE11612EVM J21 Pin Definitions
Pin# Signal Description
1 DAC5 Output pin for DAC5
2 GND Ground
3 DAC4 Output pin for DAC4
4 GND Ground
5 DAC3 Output pin for DAC3
6 GND Ground
7 DAC2 Output pin for DAC2
8 GND Ground
9 DAC1 Output pin for DAC1
10 GND Ground
11 DAC0 Output pin for DAC0
12 GND Ground

The AFE11612-SEP device contains 16 analog inputs, 12 of which are single-ended (ADC4 through ADC15) and have an input range of 0V to 5V. The other four inputs (ADC0 through ADC3) can be configured as four single-ended inputs for two fully differential channels, depending on the setup of the ADC channel registers. These signal pins are connected to J13. Table 3-5 lists the pin definitions.

Table 2-5 AFE11612EVM J13 Pin Definitions
Pin# Signal Description
1 ADC0 ADC channel 0 input
2 GND Ground
3 ADC1 ADC channel 1 input
4 GND Ground
5 ADC2 ADC channel 2 input
6 GND Ground
7 ADC3 ADC channel 3 input
8 GND Ground
9 ADC4 ADC channel 4 input
10 GND Ground
11 ADC5 ADC channel 5 input
12 GND Ground
13 ADC6 ADC channel 6 input
14 GND Ground
15 ADC7 ADC channel 7 input
16 GND Ground
17 ADC8 ADC channel 8 input
18 GND Ground
19 ADC9 ADC channel 9 input
20 GND Ground
21 ADC10 ADC channel 10 input
22 GND Ground
23 ADC11 ADC channel 11 input
24 GND Ground
25 ADC12 ADC channel 12 input
26 GND Ground
27 ADC13 ADC channel 13 input
28 GND Ground
29 ADC14 ADC channel 14 input
30 GND Ground
31 ADC15 ADC channel 15 input
32 GND Ground

Table 3-6 and Table 3-7 list the pin definitions for connectors J9 and J17, respectively, which contain all digital input and output signals for the device

Table 2-6 AFE11612EVM J9 Pin Definitions
Pin# Signal Description
1 GND Ground
2 I2C/SPI Communication mode indicator bit:
0 = I2C, 1 = SPI
3 GND Ground
4 A2 I2C address bit 2 (MSB)
5 GND Ground
6 SDO/A1 SPI output or I2C address bit 1
7 GND Ground
8 CS/A0 SPI chip select or I2C address bit 0 (LSB)
9 GND Ground
10 SCLK/SCL Clock signal for SPI or I2C serial interface
11 GND Ground
12 SDI/SDA SPI input or I2C data line
Table 2-7 AFE11612EVM J17 Pin Definitions
Pin# Signal Description
1 GND Ground
2 DAC-CLR-0 DAC clear control signal 0 (digital input, active low).
3 GND Ground
4 CNVT External ADC conversion trigger input, active low.
5 GND Ground
6 DAV Data available indicator, active low output
7 GND Ground
8 RESET Reset input, active low.
9 GND Ground
10 ALARM Global alarm, open-drain output
11 GND Ground
12 DAC-CLR-1 DAC clear control signal 1 (digital input, active low).

Table 3-8 and Table 3-9 list the pin definitions for the J18 and J19 headers, respectively, which contain the AFE11612-SEP GPIO signals. If remote temperature sensors are not needed, remote sensor channels D1+, D1–, D2+, and D2– can be configured as GPIOs on header J19.

Table 2-8 AFE11612EVM J18 Pin Definitions
Pin# Signal Description
1 GND Ground
2 GPIO-3 General-purpose I/O (GPIO3)
3 GND Ground
4 GPIO-2 General-purpose I/O (GPIO2)
5 GND Ground
6 GPIO-1 General-purpose I/O (GPIO1)
7 GND Ground
8 GPIO-0 General-purpose I/O (GPIO0)
Table 2-9 AFE11612EVM J19 Pin Definitions
Pin# Signal Description
1 GND Ground
2 D1+/GPIO-4 General-purpose I/O (GPIO4) or remote temperature sensor connection
3 GND Ground
4 D1–/GPIO-5 General-purpose I/O (GPIO5) or remote temperature sensor connection
5 GND Ground
6 D2+/GPIO-6 General-purpose I/O (GPIO6) or remote temperature sensor connection
7 GND Ground
8 D2–/GPIO-7 General-purpose I/O (GPIO7) or remote temperature sensor connection