SLAU957 June   2025 TRF1108 , TRF1208

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Setup
    3. 2.3 Interfaces
  9. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
      1. 3.2.1 HSDC Pro Overview
      2. 3.2.2 Latte Overview
        1. 3.2.2.1 Latte Shortcuts
  10. 4Implementation Results
    1. 4.1 Evaluation Setup TRF-LSC-AFE7950EVM Automatic Configuration
      1. 4.1.1 Recommended Test Environment
      2. 4.1.2 Required Hardware
      3. 4.1.3 Steps to Start Automatic Configuration
      4. 4.1.4 TXDAC Evaluation
      5. 4.1.5 RXADC and FBADC Evaluation
      6. 4.1.6 TRF-LSC-AFE7950EVM Manual Configuration
        1. 4.1.6.1 TSW14J5x DAC Pattern Setup
        2. 4.1.6.2 Connect Latte to Board
        3. 4.1.6.3 Compile Libraries
        4. 4.1.6.4 Program TRF-LSC-AFE7950EVM
        5. 4.1.6.5 Modify Configuration
      7. 4.1.7 Setup the TSW14J5x With the HSDC PRO
        1. 4.1.7.1 DAC Pattern Setup and Send
        2. 4.1.7.2 DAC Synchronization Check
        3. 4.1.7.3 ADC Data Capture
        4. 4.1.7.4 ADC Synchronization Check
    2. 4.2 Status Check and Troubleshooting Guidelines
      1. 4.2.1 EVM Status Indicators
      2. 4.2.2 TSW14J56 EVM
    3. 4.3 Performance Data and Results
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks

4.1 Evaluation Setup TRF-LSC-AFE7950EVM Automatic Configuration

This section guides the user through the sequence of steps to automatically bring up the TRF-LSC-AFE7950EVM through the automation python routine. The example used in this section is the default TRF-LSC-AFE7950EVM Mode 1. Table 4-1 lists the default Mode 1 configuration overview.

Table 4-1 TRF-LSC-AFE7950EVM Mode 1 Configuration Overview
ModeDefault Programming
TX (transmitter)4 TXDACs are enabled, DSA = 0, LMFSHd_2TX = 44210, 6 × interpolation, 491.52MSPS data rate
RX (receiver)4 RXADCs are enabled, DSA = 0, LMFSHd_2RX = 24410, 12 × decimation, 245.76MSPS data rate
FBRX (feedback receiver)Two FBADCs are enabled, DSA = 0, LMFSHd_1FB = 22210, 6 × decimation, 491.52MSPS data rate
SerDesEight lanes running at 9830.4Mbps
Data converter clock ratesFRXADC = 2949.12MSPS, FFBADC = 2949.12MSPS, FTXDAC = 8847.36MSPS
StatusRX AGC is disabled, RX, TX DSA step impairments are uncorrected, DAC in interleaved mode

Table 4-2, Table 4-3, and Table 4-4 list the TSW14J5x .ini files used to evaluate the RXADC, FBADC, and the TXDAC portions of the AFE79xx. The tables also list the associated channel mapping with respect to the TRF-LSC-AFE7950EVM.

Table 4-2 RXADC TSW14J56EVM / TSW14J57EVM INI Mapping (AFE79xx_2x2RX_24410)
ADC Channel Number in HSDC PRO ADC Panel(1)TRF-LSC-AFE7950EVM ConnectorAssociated AFE79xx Input
1,2J3, RXA_IN1RX
3,4J1, RXB_IN2RX
5,6J4, RXC_IN3RX
7,8J26, RXD_IN4RX
(1) For complex quadrature output (I/Q) of the RXADC, the odd number is the real channel, while the even number is the imaginary channel.
Table 4-3 FBADC TW14J5x INI Mapping (AFE79xx_1x2FB_44210)
ADC Channel Number in HSDC PRO ADC Panel(1)TRF-LSC-AFE7950EVM ConnectorAssociated AFE79xx Input
1,2J6, FB1_IN1FB
3,4J5 and J11, FB2_IN2FB
(1) For complex quadrature output (I/Q) of the FBADC, the odd number is the real channel, while the even number is the imaginary channel.
Table 4-4 TXDAC TSW14J5x INI Mapping (AFE79xx_2x2TX_44210)
DAC Channel Number in HSDC PRO DAC Panel(1)AFE79xx EVM ConnectorAssociated AFE79xx Input
1,2J10, TXA_OUT1TX
3,4J7, TXB_OUT2TX
5,6J21, TXC_OUT3TX
7,8J22, TXD_OUT4TX
(1) For complex quadrature output (I/Q) of the TXDAC, the odd number is the real channel, while the even number is the imaginary channel.