SLAU957 June   2025 TRF1108 , TRF1208

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Power Requirements
    2. 2.2 Setup
    3. 2.3 Interfaces
  9. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
      1. 3.2.1 HSDC Pro Overview
      2. 3.2.2 Latte Overview
        1. 3.2.2.1 Latte Shortcuts
  10. 4Implementation Results
    1. 4.1 Evaluation Setup TRF-LSC-AFE7950EVM Automatic Configuration
      1. 4.1.1 Recommended Test Environment
      2. 4.1.2 Required Hardware
      3. 4.1.3 Steps to Start Automatic Configuration
      4. 4.1.4 TXDAC Evaluation
      5. 4.1.5 RXADC and FBADC Evaluation
      6. 4.1.6 TRF-LSC-AFE7950EVM Manual Configuration
        1. 4.1.6.1 TSW14J5x DAC Pattern Setup
        2. 4.1.6.2 Connect Latte to Board
        3. 4.1.6.3 Compile Libraries
        4. 4.1.6.4 Program TRF-LSC-AFE7950EVM
        5. 4.1.6.5 Modify Configuration
      7. 4.1.7 Setup the TSW14J5x With the HSDC PRO
        1. 4.1.7.1 DAC Pattern Setup and Send
        2. 4.1.7.2 DAC Synchronization Check
        3. 4.1.7.3 ADC Data Capture
        4. 4.1.7.4 ADC Synchronization Check
    2. 4.2 Status Check and Troubleshooting Guidelines
      1. 4.2.1 EVM Status Indicators
      2. 4.2.2 TSW14J56 EVM
    3. 4.3 Performance Data and Results
  11. 5Hardware Design Files
    1. 5.1 Schematics
    2. 5.2 PCB Layouts
    3. 5.3 Bill of Materials (BOM)
  12. 6Additional Information
    1. 6.1 Trademarks

4.1.5 RXADC and FBADC Evaluation

  1. Before starting the RXADC and FBADC performance capture, set up the HSDC PRO test option. Go to Test Options to enter the Filter Parameters menu. By default, there are 25 bins to remove on either side of fundamental and 25 bins near dc to remove. Per Figure 4-9, change the number of bins to remove on either side of fundamental to 100 bins.
    1. With a data rate of 245.76MSPS for RXADC at 16384 sample points, 1.5MHz of bins on either side of the fundamental are removed.
    2. With a data rate of 491.52MSPS for FBADC at 16384 sample points, 3.0MHz of bins on either side of the fundamental are removed.
    3. The number of bins to remove is a standard recommendation from TI. This recommendation removes the effect of the ADC sampling clock in-band phase noise from affecting the broadband noise used to calculate the SNR through the FFT engine. Adjust the number of bins based on the end-application standard.
    TRF-LSC-AFE7950EVM HSDC PRO ADC Performance FFT Binning Configuration Figure 4-9 HSDC PRO ADC Performance FFT Binning Configuration
  2. Connect the RF signal generator output to J3 (RXA_IN), J1 (RXB_IN), and J4 (RXC_IN) to capture the RF input to the ADC. On the HSDC PRO application, press the Capture button to capture the ADC data.
  3. Feed in a tone of 10MHz offset from the channel frequency. For example, feed 2210MHz to RXA_IN, 5010MHz to RXB_IN, and 6010MHz to FB1_IN. Set the signal level to get approximately –4 dBFS at the ADC output. The gain is different for various channels; therefore, the signal generator output levels are different.
    1. RXA_IN is channel 1 and 2 in FFT channel selection
    2. RXB_IN is channel 3 and 4 in FFT channel selection
    3. FB1_IN is channel 1 and 2 in FFT under FB mode channel selection
  4. Similarly, feed 7510MHz to RXC_IN and 6010MHz to FB2_IN. Set the signal level to get approximately –4dBFS at the ADC output.
    1. RXC_IN is channel 5 and 6 in FFT channel selection
    2. FB2_IN is channel 3 and 4 in FFT under FB mode channel selection
  5. For the feedback ADC, execute the following commands or execute AFE79xx_FB_Capture.py through the F5 key. 
    1. ###### Configure FB-ADC 
####################################################
AFE.TOP.overrideTdd(0,3,0)
hsdcparam.fb.Datarate=sysParams.FadcFb/sysParams.ddcFactorFb[0]*1e6confighsdcpro().fb()