SLAU965 May   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Troubleshooting
  8. 2Hardware
    1. 2.1 Hardware Setup
    2. 2.2 Detailed Operation
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 Board Layouts
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1. 4.1 Trademarks

Detailed Operation

The TAS5830EVM only requires a single supply to operate. Users can select three different audio sources:

  1. Toggle the S2 switch to XMOS to stream audio through the Windows Media Player.
  2. Toggle the S2 switch to SPDIF to stream audio through a DVD player with an optical cable or an analog cable.
  3. Use jumpers to insert external I2S signals if an external digital audio source such as Programmable Serial Interface Adapter (PSIA) from Audio Precision is desired.

Both 3.3V and 1.8V DVDD and IOVDD are supported with TAS5830EVM. Use jumper (J26) to select accordingly based on requirement.

The TAS5830EVM provides optional onboard LM5155 boost Class-H evaluation or external customer system boost with Class-H control:

  1. Onboard LM5155 boost Class-H evaluation
    • 9V battery power input through J12 and J13. Bypass external PVDD by removing J18
    • TAS5830 PVDD is from LM5155 boost output: J14 - IN, J18 - OUT
    • TAS5830 Class-H pin routes to LM5155 FB pin: J15 - IN, J16 - OUT
  2. External customer system boost with Class-H control
    • TAS5830 Class-H pin routes for external customer system boost FB control through TP7 FB and TP8 GND: J15 - OUT, J16 - OUT
    • Customer system boost output for TAS5830 PVDD through J17 PVDD and J20 GND: J14 - OUT, J18 - IN

The USB connection is also used to provide I2C communications with the two TAS5830 devices on the EVM. The PurePath™ Console 3 (PPC3) is the software tool which can initialize and operate this EVM.

Alternatively, the TAS5830 has an optional Hardware Control Mode to configure switching frequency, analog gain, BTL/PBTL mode and cycle-by-cycle current limit through pin configuration. Hardware Control Mode can be enabled by modifying J8 ADR/HW to HW, J10 SDA/HW_SEL0 to the desired mode according to Table 2-3, and J11 SCK/HW_SEL1 to the desired mode according to Table 2-4.

Table 2-3 Hardware Control - HW_SEL0 Pin5
R11 (GND)R9 (DVDD)Analog GainH-Bridge Output Configuration
DNP33.0VP/FSBTL
1kΩDNP23.4VP/FSBTL
4.7kΩDNP16.4VP/FSBTL
15kΩDNP8.3VP/FSBTL
DNP33kΩ8.3VP/FSPBTL
DNP6.8kΩ16.4VP/FSPBTL
DNP1.5kΩ23.4VP/FSPBTL
DNP33.0VP/FSPBTL
Table 2-4 Hardware Control - HW_SEL1 Pin6
R10 (GND)R8 (DVDD)FSW & Class D Loop BandwidthCycle-By-Cycle Current Limit ThresholdSpread SpectrumModulation
DNP768kHz FSW, 175kHz BWCBC Threshold = 80% OCPDisable1SPW
1kΩDNP768kHz FSW, 175kHz BWCBC DisableDisable1SPW
4.7kΩDNP768kHz FSW, 175kHz BWCBC Threshold = 40% OCPDisable1SPW
15kΩDNP768kHz FSW, 175kHz BWCBC Threshold = 60% OCPDisable1SPW
DNP33kΩ480kHz FSW, 100 kHz BWCBC DisableEnableBD
DNP6.8kΩ480kHz FSW, 100kHz BWCBC Threshold = 80% OCPEnableBD
DNP1.5kΩ480kHz FSW, 100kHz BWCBC Threshold = 40% OCPEnableBD
DNP480kHz FSW, 100kHz BWCBC Threshold = 60% OCPEnableBD