SLAU966 February   2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0C1106-Q1 , MSPM0G1106 , MSPM0G1107 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2228

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of NXP M0 MCUs to MSPM0
  5. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 MCUXpresso IDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 MCUXpresso Code Configuration Tool vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Memory Banks
        2. 3.2.2.2 Flash Memory Regions
        3. 3.2.2.3 NONMAIN Memory
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Power Modes
      3. 3.5.3 Entering Lower-Power Modes
    6. 3.6 Interrupt and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
      2. 3.6.2 Event Handler and Extended Interrupt and Event Controller (EXTI)
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Bootstrap Loader (BSL) Programming Options
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6References

3.4 Clocks Summary and Comparison

NXP's MCUs and MSPM0 both contain internal oscillators that source primary clocks. The clocks can be divided to source other clocks and be distributed across the multitude of peripherals.

Table 3-5 Oscillator Comparisons
Oscillator S32K1xx KEA128x KM35x MSPM0G/L

MSPM0C
Internal RC Fast IRC, Slow IRC N/A Internal RC (4MHz) SYSOSC(1) SYSOSC (24MHz)
Full Swing Crystal SOSC OSCCLK HFXT N/A
Internal RC LP0 128kHZ IRC 32kHz LFOSC 32kHz
Low Frequency Crystal N/A N/A OSC32K LFXT - 32kHz N/A
Low Power Crystal N/A 1kHZ LPO N/A LFXT - 32kHz N/A
(1) SYSOSC is programmable to be 32MHz, 24MHz, 16MHz, or 4MHz.
Table 3-6 Clock Comparison
Clock S32K1xx KEA128x KM35 MSPM0G MSPM0L/C
System SOSC ICSOUTCLK MCGOUTCLK SYSOSC (4-32MHz) SYSOSC (24MHz)
SPLLDIV1 N/A MCGPLLCLK SYSPLLCLK1 N/A
SPLLDIV2 N/A MCGFLLCLK SYSPLLCLK0 N/A
N/A SYSPLLCLK2x1 N/A
Core / Bus Clock CORE_CLK ICSOUTCLK MCGOUTCLK BUSCLK/ULPCLK2 BUSCLK/ULPCLK2
Slow Internal Clock SIRC (8MHz) IRC (37.5kHz) IRC (32kHz) LFOSC (32kHz)
Fast Internal Clock FIRC (48MHz) N/A IRC (4MHz) SYSOSC
Low Power Clock LPO (128 kHz) LP0CLK LPO (1kHz) LFCLK (32kHz)
RTC Clock N/A OSCERCLK IRTC/OSC32KCLK RTCCLK N/A
  1. SYSPLLCLK2x is twice the speed of the output of the PLL module and can be divided down.
  2. BUSCLK depends on the Power Domain. For Power Domain 0, BUSCLK is ULPCLK. For Power Domain 1, BUSCLK is MCLK.
Table 3-7 Peripheral Clock Sources
Peripheral S32K1xx KEA128x KM35x MSPM0G MSPM0L/C
RTC LP01K_CLK, RTC_CLK BUS_CLK,LPOCLK,ICSIRCLK,OSCERCLK EXTAL32 LFCLK (LFOSC, LFXT) N/A
UART BUSCLK,SOSCDIV2_CLK,FIRCDIV2_CLK,SPLLDIV2_CLK BUSCLK BUSCLK BUSCLK, ULPCLK,MFCLK, LFCLK BUSCLK, ULPCLK,MFCLK, LFCLK
SPI BUSCLK,SOSCDIV2_CLK,FIRCDIV2_CLK,SPLLDIV2_CLK BUSCLK BUSCLK BUSCLK, MFCLK, LFCLK BUSCLK, ULPCLK,MFCLK, LFCLK
I2C BUSCLK BUSCLK BUSCLK, MFCLK BUSCLK, ULPCLK,MFCLK, LFCLK
ADC BUSCLK,OSCERCLK,ADACK OSCERCLK,MCGPLLCLK ULPCLK, HFCLK, SYSOSC SYSOSC, ULPCLK
LPTIM 1/2 TIMER_CLK LPO, OSCERCLK,MCGIRCLK,ERCLK32K LFCLK, ULPCLK, LFCLK_IN ULPCLK, LFCLK
TIMERS SYS_CLK,SOSCDIV1_CLK,FIRCDIV1_CLK,SPLLDIV1_CLK TIMER_CLK,ICSFFCLK BUSCLK BUSCLK, MFCLK, LFCLK BUSCLK, ULPCLK,MFCLK, LFCLK

The device-specific TRM for each family has a clock tree to help visualize the clock system. Sysconfig can assist with the options for clock division and sourcing for peripherals.