SLAZ105Z October   2012  – May 2021 CC430F6147

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      RGC64
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  AES1
    5. 6.5  BSL7
    6. 6.6  BSL14
    7. 6.7  COMP10
    8. 6.8  CPU21
    9. 6.9  CPU22
    10. 6.10 CPU36
    11. 6.11 CPU40
    12. 6.12 CPU46
    13. 6.13 CPU47
    14. 6.14 DMA4
    15. 6.15 DMA7
    16. 6.16 DMA10
    17. 6.17 EEM17
    18. 6.18 EEM19
    19. 6.19 EEM23
    20. 6.20 JTAG26
    21. 6.21 JTAG27
    22. 6.22 LCDB5
    23. 6.23 LCDB6
    24. 6.24 PMM11
    25. 6.25 PMM12
    26. 6.26 PMM14
    27. 6.27 PMM15
    28. 6.28 PMM18
    29. 6.29 PMM20
    30. 6.30 PMM26
    31. 6.31 PORT15
    32. 6.32 PORT19
    33. 6.33 PORT29
    34. 6.34 RF1A1
    35. 6.35 RF1A2
    36. 6.36 RF1A3
    37. 6.37 RF1A5
    38. 6.38 RF1A6
    39. 6.39 RF1A8
    40. 6.40 SYS12
    41. 6.41 SYS16
    42. 6.42 UCS11
    43. 6.43 USCI26
    44. 6.44 USCI30
    45. 6.45 USCI34
    46. 6.46 USCI35
    47. 6.47 USCI39
    48. 6.48 USCI40
  7. 7Revision History

PMM11

PMM Module

Category

Functional

Function

MCLK comes up fast on exit from LPM3 and LPM4

Description

The DCO exceeds the programmed frequency of operation on exit from LPM3 and LPM4 for up to 6 us. This behavior is masked from affecting code execution by default: SVSL and SVML run in normal-performance mode and mask CPU execution for 150 us on wakeup from LPM3 and LPM4. However ,when the low-side SVS and the SVM are disabled or are operating in full-performance mode (SVMLE= 0 and SVSLE= 0, or SVMLFP= 1 and SVSLFP= 1) AND MCLK is sourced from the internal DCO running over 5 MHz, 7.5 MHz,10 MHz,or 12.5 MHz at core voltage levels 0, 1, 2, and 3, respectively, the mask lasts only 2 us. MCLK is, therefore, susceptible to run out of spec for 4 us.

Workaround

Set the MCLK divide bits in the Unified Clock System Control 5 Register (UCSCTL5) to divide MCLK by two prior to entering LPM3 or LPM4 (set DIVMx= 001). This prevents MCLK from running out of spec when the CPU wakes from the low-power mode. Following the wakeup fromthe low-power mode, wait 32, 48, 80, or 100 cycles for core voltage levels 0, 1, 2, and 3, respectively, before resetting DIVM xto zero and running MCLK at full speed [for example, __delay_cycles(100)]