SLAZ151H October   2012  – May 2021 MSP430F2001

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PW14
      2.      N14
      3.      RSA16
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  BCL9
    2. 6.2  BCL10
    3. 6.3  BCL11
    4. 6.4  BCL12
    5. 6.5  BCL13
    6. 6.6  BCL14
    7. 6.7  CPU4
    8. 6.8  EEM20
    9. 6.9  FLASH16
    10. 6.10 FLASH22
    11. 6.11 PORT10
    12. 6.12 SBW1
    13. 6.13 SYS15
    14. 6.14 TA12
    15. 6.15 TA16
    16. 6.16 TA17
    17. 6.17 TA21
    18. 6.18 TAB22
    19. 6.19 XOSC5
    20. 6.20 XOSC8
  7. 7Revision History

6.1 BCL9

BCL Module

Category

Functional

Function

ACLK divider modifications require delay before entering LPM3

Description

After modifying the DIVAx bits, immediately entering LPM3 can cause the modification to be ignored and the divider settings not to take effect. Reading back the DIVAx bits will indicate the intended setting even when the divider has not been correctly applied.

Workaround

When the DIVAx bits are modified, a delay of one complete ACLK (VLO or LFXT1CLK) period must elapse before entering LPM3. The delay is only necessary the first time LPM3 is entered after the DIVAx bits are modified. After the one-period delay, LPM3 may be entered and exited normally without additional delays.