SLAZ493AA December   2012  – September 2021 MSP430F5659

 

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6.31 PORT26

PORT Module

Category

Functional

Function

Incorrect values for P1.1 / P1.2 input pins during power-up

Description

If P1.1/P1.2 is pulled up externally to DVCC during power-up the logical HIGH value might not be read correct by the device (ZERO is read instead of ONE).

Workaround

1) Switch the P1.1/P1.2 Port to logical ZERO after power cycle by:
    a) Switch critical GPIO to output-low (with series resistance to limit current) or
    b) Remove external pull up connection to pull GPIO via internal pull-down

OR

2) Use different GPIOs (not P1.1 & P1.2)

OR

3) Change the polarity of the logical check in SW (enable internal pull-up resistor for the GPIO and pull the external pin to DVSS)