1 Introduction

RS-485 is a long-distance differential interface that can communicate at relatively high speeds with enhanced signal integrity. When designing for a RS-485 transceiver in a system, it can be efficient to minimize the amount of logic lines that connect to each transceiver where possible. A microcontroller can have limited GPIOs to control the RS-485 transceiver. One method to reduce the logic lines is to combine the driver and receiver enable pin as shown in Figure 1-1.

Figure 1-1 Shorted nRE and DE Pins on a Half-duplex RS-485 Transceiver

When the driver and receiver enable pins are shorted together, there are particular setups that can cause glitches. If the RC time constant on the bus is long enough, a low voltage can be read on the receiver pin right after the device is switched from transmitting to receiving. This voltage low can be read as a 0 bit. Because the R line is held high, this 0 bit can be interpreted as a start condition by the UART protocol.

This document includes the theoretical analysis behind these undesired behaviors. A half-duplex RS-485 transceiver is tested to demonstrate the majority of RS-485 transceivers. A timer-based fail-safe transceiver is also tested as the glitch can trigger this feature. Specifically, THVD1400 is representative of all general half-duplex devices in testing, and THVD2410 is tested to demonstrate the timer-based fail-safe scenario. Finally, a combination of workarounds are provided, followed with test data showcasing this.